1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007-2012 3*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4*4882a593Smuzhiyun * Tom Cubie <tangliang@allwinnertech.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun #include <asm/arch/clock.h> 14*4882a593Smuzhiyun #include <asm/arch/gpio.h> 15*4882a593Smuzhiyun #include <asm/arch/prcm.h> 16*4882a593Smuzhiyun #include <asm/arch/gtbus.h> 17*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 18*4882a593Smuzhiyun clock_init_sec(void)19*4882a593Smuzhiyun__weak void clock_init_sec(void) 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun gtbus_init(void)23*4882a593Smuzhiyun__weak void gtbus_init(void) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun } 26*4882a593Smuzhiyun clock_init(void)27*4882a593Smuzhiyunint clock_init(void) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 30*4882a593Smuzhiyun clock_init_safe(); 31*4882a593Smuzhiyun gtbus_init(); 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun clock_init_uart(); 34*4882a593Smuzhiyun clock_init_sec(); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun return 0; 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* These functions are shared between various SoCs so put them here. */ 40*4882a593Smuzhiyun #if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I clock_twi_onoff(int port,int state)41*4882a593Smuzhiyunint clock_twi_onoff(int port, int state) 42*4882a593Smuzhiyun { 43*4882a593Smuzhiyun struct sunxi_ccm_reg *const ccm = 44*4882a593Smuzhiyun (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun if (port == 5) { 47*4882a593Smuzhiyun if (state) 48*4882a593Smuzhiyun prcm_apb0_enable( 49*4882a593Smuzhiyun PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); 50*4882a593Smuzhiyun else 51*4882a593Smuzhiyun prcm_apb0_disable( 52*4882a593Smuzhiyun PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); 53*4882a593Smuzhiyun return 0; 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* set the apb clock gate and reset for twi */ 57*4882a593Smuzhiyun if (state) { 58*4882a593Smuzhiyun setbits_le32(&ccm->apb2_gate, 59*4882a593Smuzhiyun CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); 60*4882a593Smuzhiyun setbits_le32(&ccm->apb2_reset_cfg, 61*4882a593Smuzhiyun 1 << (APB2_RESET_TWI_SHIFT + port)); 62*4882a593Smuzhiyun } else { 63*4882a593Smuzhiyun clrbits_le32(&ccm->apb2_reset_cfg, 64*4882a593Smuzhiyun 1 << (APB2_RESET_TWI_SHIFT + port)); 65*4882a593Smuzhiyun clrbits_le32(&ccm->apb2_gate, 66*4882a593Smuzhiyun CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); 67*4882a593Smuzhiyun } 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun return 0; 70*4882a593Smuzhiyun } 71*4882a593Smuzhiyun #endif 72