1 /*
2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3 *
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
7 *
8 * Some init for sunxi platform.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13 #include <common.h>
14 #include <mmc.h>
15 #include <i2c.h>
16 #include <serial.h>
17 #ifdef CONFIG_SPL_BUILD
18 #include <spl.h>
19 #endif
20 #include <asm/gpio.h>
21 #include <asm/io.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/spl.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <asm/arch/tzpc.h>
28 #include <asm/arch/mmc.h>
29
30 #include <linux/compiler.h>
31
32 struct fel_stash {
33 uint32_t sp;
34 uint32_t lr;
35 uint32_t cpsr;
36 uint32_t sctlr;
37 uint32_t vbar;
38 uint32_t cr;
39 };
40
41 struct fel_stash fel_stash __attribute__((section(".data")));
42
43 #ifdef CONFIG_ARM64
44 #include <asm/armv8/mmu.h>
45
46 static struct mm_region sunxi_mem_map[] = {
47 {
48 /* SRAM, MMIO regions */
49 .virt = 0x0UL,
50 .phys = 0x0UL,
51 .size = 0x40000000UL,
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
53 PTE_BLOCK_NON_SHARE
54 }, {
55 /* RAM */
56 .virt = 0x40000000UL,
57 .phys = 0x40000000UL,
58 .size = 0x80000000UL,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
60 PTE_BLOCK_INNER_SHARE
61 }, {
62 /* List terminator */
63 0,
64 }
65 };
66 struct mm_region *mem_map = sunxi_mem_map;
67 #endif
68
gpio_init(void)69 static int gpio_init(void)
70 {
71 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
72 #if defined(CONFIG_MACH_SUN4I) || \
73 defined(CONFIG_MACH_SUN7I) || \
74 defined(CONFIG_MACH_SUN8I_R40)
75 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
76 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
77 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
78 #endif
79 #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
80 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
81 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
82 #else
83 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
84 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
85 #endif
86 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
87 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
88 defined(CONFIG_MACH_SUN7I) || \
89 defined(CONFIG_MACH_SUN8I_R40))
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
92 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
93 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
96 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
97 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
100 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
101 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
102 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
103 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
104 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
105 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
106 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
107 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
108 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
109 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
111 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
112 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
113 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
115 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
116 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
117 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
118 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
119 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
120 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
121 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
122 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
123 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
124 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
125 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
126 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
127 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
128 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
129 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
132 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
133 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
135 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
136 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
137 #else
138 #error Unsupported console port number. Please fix pin mux settings in board.c
139 #endif
140
141 return 0;
142 }
143
144 #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
spl_board_load_image(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)145 static int spl_board_load_image(struct spl_image_info *spl_image,
146 struct spl_boot_device *bootdev)
147 {
148 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
149 return_to_fel(fel_stash.sp, fel_stash.lr);
150
151 return 0;
152 }
153 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
154 #endif
155
s_init(void)156 void s_init(void)
157 {
158 /*
159 * Undocumented magic taken from boot0, without this DRAM
160 * access gets messed up (seems cache related).
161 * The boot0 sources describe this as: "config ema for cache sram"
162 */
163 #if defined CONFIG_MACH_SUN6I
164 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
165 #elif defined CONFIG_MACH_SUN8I
166 __maybe_unused uint version;
167
168 /* Unlock sram version info reg, read it, relock */
169 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
170 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
171 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
172
173 /*
174 * Ideally this would be a switch case, but we do not know exactly
175 * which versions there are and which version needs which settings,
176 * so reproduce the per SoC code from the BSP.
177 */
178 #if defined CONFIG_MACH_SUN8I_A23
179 if (version == 0x1650)
180 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
181 else /* 0x1661 ? */
182 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
183 #elif defined CONFIG_MACH_SUN8I_A33
184 if (version != 0x1667)
185 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
186 #endif
187 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
188 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
189 #endif
190
191 #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
192 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
193 asm volatile(
194 "mrc p15, 0, r0, c1, c0, 1\n"
195 "orr r0, r0, #1 << 6\n"
196 "mcr p15, 0, r0, c1, c0, 1\n"
197 ::: "r0");
198 #endif
199 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
200 /* Enable non-secure access to some peripherals */
201 tzpc_init();
202 #endif
203
204 clock_init();
205 timer_init();
206 gpio_init();
207 #ifndef CONFIG_DM_I2C
208 i2c_init_board();
209 #endif
210 eth_init_board();
211 }
212
213 #ifdef CONFIG_SPL_BUILD
214 DECLARE_GLOBAL_DATA_PTR;
215
216 /* The sunxi internal brom will try to loader external bootloader
217 * from mmc0, nand flash, mmc2.
218 */
spl_boot_device(void)219 u32 spl_boot_device(void)
220 {
221 int boot_source;
222
223 /*
224 * When booting from the SD card or NAND memory, the "eGON.BT0"
225 * signature is expected to be found in memory at the address 0x0004
226 * (see the "mksunxiboot" tool, which generates this header).
227 *
228 * When booting in the FEL mode over USB, this signature is patched in
229 * memory and replaced with something else by the 'fel' tool. This other
230 * signature is selected in such a way, that it can't be present in a
231 * valid bootable SD card image (because the BROM would refuse to
232 * execute the SPL in this case).
233 *
234 * This checks for the signature and if it is not found returns to
235 * the FEL code in the BROM to wait and receive the main u-boot
236 * binary over USB. If it is found, it determines where SPL was
237 * read from.
238 */
239 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
240 return BOOT_DEVICE_BOARD;
241
242 boot_source = readb(SPL_ADDR + 0x28);
243 switch (boot_source) {
244 case SUNXI_BOOTED_FROM_MMC0:
245 return BOOT_DEVICE_MMC1;
246 case SUNXI_BOOTED_FROM_NAND:
247 return BOOT_DEVICE_NAND;
248 case SUNXI_BOOTED_FROM_MMC2:
249 return BOOT_DEVICE_MMC2;
250 case SUNXI_BOOTED_FROM_SPI:
251 return BOOT_DEVICE_SPI;
252 }
253
254 panic("Unknown boot source %d\n", boot_source);
255 return -1; /* Never reached */
256 }
257
258 /* No confirmation data available in SPL yet. Hardcode bootmode */
spl_boot_mode(const u32 boot_device)259 u32 spl_boot_mode(const u32 boot_device)
260 {
261 return MMCSD_MODE_RAW;
262 }
263
board_init_f(ulong dummy)264 void board_init_f(ulong dummy)
265 {
266 spl_init();
267 preloader_console_init();
268
269 #ifdef CONFIG_SPL_I2C_SUPPORT
270 /* Needed early by sunxi_board_init if PMU is enabled */
271 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
272 #endif
273 sunxi_board_init();
274 }
275 #endif
276
reset_cpu(ulong addr)277 void reset_cpu(ulong addr)
278 {
279 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
280 static const struct sunxi_wdog *wdog =
281 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
282
283 /* Set the watchdog for its shortest interval (.5s) and wait */
284 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
285 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
286
287 while (1) {
288 /* sun5i sometimes gets stuck without this */
289 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
290 }
291 #elif defined(CONFIG_SUNXI_GEN_SUN6I)
292 static const struct sunxi_wdog *wdog =
293 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
294
295 /* Set the watchdog for its shortest interval (.5s) and wait */
296 writel(WDT_CFG_RESET, &wdog->cfg);
297 writel(WDT_MODE_EN, &wdog->mode);
298 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
299 while (1) { }
300 #endif
301 }
302
303 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
enable_caches(void)304 void enable_caches(void)
305 {
306 /* Enable D-cache. I-cache is already enabled in start.S */
307 dcache_enable();
308 }
309 #endif
310