1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2015
3*4882a593Smuzhiyun * Kamil Lulko, <kamil.lulko@gmail.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/armv7m_mpu.h>
11*4882a593Smuzhiyun #include <asm/arch/stm32.h>
12*4882a593Smuzhiyun
get_cpu_rev(void)13*4882a593Smuzhiyun u32 get_cpu_rev(void)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun return 0;
16*4882a593Smuzhiyun }
17*4882a593Smuzhiyun
arch_cpu_init(void)18*4882a593Smuzhiyun int arch_cpu_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun int i;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct mpu_region_config stm32_region_config[] = {
23*4882a593Smuzhiyun { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
24*4882a593Smuzhiyun O_I_WB_RD_WR_ALLOC, REGION_4GB },
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
27*4882a593Smuzhiyun STRONG_ORDER, REGION_512MB },
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
30*4882a593Smuzhiyun DEVICE_NON_SHARED, REGION_512MB },
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun { 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
33*4882a593Smuzhiyun DEVICE_NON_SHARED, REGION_512MB },
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
36*4882a593Smuzhiyun STRONG_ORDER, REGION_512MB },
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun disable_mpu();
40*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
41*4882a593Smuzhiyun mpu_config(&stm32_region_config[i]);
42*4882a593Smuzhiyun enable_mpu();
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
s_init(void)47*4882a593Smuzhiyun void s_init(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun }
50