1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 3*4882a593Smuzhiyun * Kamil Lulko, <kamil.lulko@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/armv7m.h> 11*4882a593Smuzhiyun #include <asm/arch/stm32.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define RCC_APB1ENR_TIM2EN (1 << 0) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct stm32_tim2_5 { 20*4882a593Smuzhiyun u32 cr1; 21*4882a593Smuzhiyun u32 cr2; 22*4882a593Smuzhiyun u32 smcr; 23*4882a593Smuzhiyun u32 dier; 24*4882a593Smuzhiyun u32 sr; 25*4882a593Smuzhiyun u32 egr; 26*4882a593Smuzhiyun u32 ccmr1; 27*4882a593Smuzhiyun u32 ccmr2; 28*4882a593Smuzhiyun u32 ccer; 29*4882a593Smuzhiyun u32 cnt; 30*4882a593Smuzhiyun u32 psc; 31*4882a593Smuzhiyun u32 arr; 32*4882a593Smuzhiyun u32 reserved1; 33*4882a593Smuzhiyun u32 ccr1; 34*4882a593Smuzhiyun u32 ccr2; 35*4882a593Smuzhiyun u32 ccr3; 36*4882a593Smuzhiyun u32 ccr4; 37*4882a593Smuzhiyun u32 reserved2; 38*4882a593Smuzhiyun u32 dcr; 39*4882a593Smuzhiyun u32 dmar; 40*4882a593Smuzhiyun u32 or; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define TIM_CR1_CEN (1 << 0) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define TIM_EGR_UG (1 << 0) 46*4882a593Smuzhiyun timer_init(void)47*4882a593Smuzhiyunint timer_init(void) 48*4882a593Smuzhiyun { 49*4882a593Smuzhiyun struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1)) 54*4882a593Smuzhiyun writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1, 55*4882a593Smuzhiyun &tim->psc); 56*4882a593Smuzhiyun else 57*4882a593Smuzhiyun writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1, 58*4882a593Smuzhiyun &tim->psc); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun writel(0xFFFFFFFF, &tim->arr); 61*4882a593Smuzhiyun writel(TIM_CR1_CEN, &tim->cr1); 62*4882a593Smuzhiyun setbits_le32(&tim->egr, TIM_EGR_UG); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun gd->arch.tbl = 0; 65*4882a593Smuzhiyun gd->arch.tbu = 0; 66*4882a593Smuzhiyun gd->arch.lastinc = 0; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun return 0; 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun get_timer(ulong base)71*4882a593Smuzhiyunulong get_timer(ulong base) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base; 74*4882a593Smuzhiyun } 75*4882a593Smuzhiyun get_ticks(void)76*4882a593Smuzhiyununsigned long long get_ticks(void) 77*4882a593Smuzhiyun { 78*4882a593Smuzhiyun struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; 79*4882a593Smuzhiyun u32 now; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun now = readl(&tim->cnt); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun if (now >= gd->arch.lastinc) 84*4882a593Smuzhiyun gd->arch.tbl += (now - gd->arch.lastinc); 85*4882a593Smuzhiyun else 86*4882a593Smuzhiyun gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun gd->arch.lastinc = now; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun return gd->arch.tbl; 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun reset_timer(void)93*4882a593Smuzhiyunvoid reset_timer(void) 94*4882a593Smuzhiyun { 95*4882a593Smuzhiyun struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun gd->arch.lastinc = readl(&tim->cnt); 98*4882a593Smuzhiyun gd->arch.tbl = 0; 99*4882a593Smuzhiyun } 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* delay x useconds */ __udelay(ulong usec)102*4882a593Smuzhiyunvoid __udelay(ulong usec) 103*4882a593Smuzhiyun { 104*4882a593Smuzhiyun unsigned long long start; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun start = get_ticks(); /* get current timestamp */ 107*4882a593Smuzhiyun while ((get_ticks() - start) < usec) 108*4882a593Smuzhiyun ; /* loop till time has passed */ 109*4882a593Smuzhiyun } 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * This function is derived from PowerPC code (timebase clock frequency). 113*4882a593Smuzhiyun * On ARM it returns the number of timer ticks per second. 114*4882a593Smuzhiyun */ get_tbclk(void)115*4882a593Smuzhiyunulong get_tbclk(void) 116*4882a593Smuzhiyun { 117*4882a593Smuzhiyun return CONFIG_SYS_HZ_CLOCK; 118*4882a593Smuzhiyun } 119