xref: /OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/timer.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/arch/timer.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define TIMER_LOAD_VAL		0xFFFFFFFF
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun  * Timer initialization
17*4882a593Smuzhiyun  */
timer_init(void)18*4882a593Smuzhiyun int timer_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun 	writel(TIMER_LOAD_VAL, &timer_base->load_val);
21*4882a593Smuzhiyun 	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
22*4882a593Smuzhiyun 	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
23*4882a593Smuzhiyun 	return 0;
24*4882a593Smuzhiyun }
25