1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <asm/arch/system_manager.h> 10*4882a593Smuzhiyun #include <asm/arch/fpga_manager.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun static struct socfpga_system_manager *sysmgr_regs = 15*4882a593Smuzhiyun (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. 19*4882a593Smuzhiyun * The value is not wrote to SYSMGR.FPGAINTF.MODULE but 20*4882a593Smuzhiyun * CONFIG_SYSMGR_ISWGRP_HANDOFF. 21*4882a593Smuzhiyun */ populate_sysmgr_fpgaintf_module(void)22*4882a593Smuzhiyunstatic void populate_sysmgr_fpgaintf_module(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun u32 handoff_val = 0; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* ISWGRP_HANDOFF_FPGAINTF */ 27*4882a593Smuzhiyun writel(0, &sysmgr_regs->iswgrp_handoff[2]); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Enable the signal for those HPS peripherals that use FPGA. */ 30*4882a593Smuzhiyun if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) 31*4882a593Smuzhiyun handoff_val |= SYSMGR_FPGAINTF_NAND; 32*4882a593Smuzhiyun if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) 33*4882a593Smuzhiyun handoff_val |= SYSMGR_FPGAINTF_EMAC1; 34*4882a593Smuzhiyun if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) 35*4882a593Smuzhiyun handoff_val |= SYSMGR_FPGAINTF_SDMMC; 36*4882a593Smuzhiyun if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) 37*4882a593Smuzhiyun handoff_val |= SYSMGR_FPGAINTF_EMAC0; 38*4882a593Smuzhiyun if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) 39*4882a593Smuzhiyun handoff_val |= SYSMGR_FPGAINTF_SPIM0; 40*4882a593Smuzhiyun if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) 41*4882a593Smuzhiyun handoff_val |= SYSMGR_FPGAINTF_SPIM1; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE 44*4882a593Smuzhiyun based on pinmux setting */ 45*4882a593Smuzhiyun setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); 48*4882a593Smuzhiyun if (fpgamgr_test_fpga_ready()) { 49*4882a593Smuzhiyun /* Enable the required signals only */ 50*4882a593Smuzhiyun writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module); 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun } 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Configure all the pin muxes 56*4882a593Smuzhiyun */ sysmgr_pinmux_init(void)57*4882a593Smuzhiyunvoid sysmgr_pinmux_init(void) 58*4882a593Smuzhiyun { 59*4882a593Smuzhiyun u32 regs = (u32)&sysmgr_regs->emacio[0]; 60*4882a593Smuzhiyun const u8 *sys_mgr_init_table; 61*4882a593Smuzhiyun unsigned int len; 62*4882a593Smuzhiyun int i; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun sysmgr_get_pinmux_table(&sys_mgr_init_table, &len); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun for (i = 0; i < len; i++) { 67*4882a593Smuzhiyun writel(sys_mgr_init_table[i], regs); 68*4882a593Smuzhiyun regs += sizeof(regs); 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun populate_sysmgr_fpgaintf_module(); 72*4882a593Smuzhiyun } 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * This bit allows the bootrom to configure the IOs after a warm reset. 76*4882a593Smuzhiyun */ sysmgr_config_warmrstcfgio(int enable)77*4882a593Smuzhiyunvoid sysmgr_config_warmrstcfgio(int enable) 78*4882a593Smuzhiyun { 79*4882a593Smuzhiyun if (enable) 80*4882a593Smuzhiyun setbits_le32(&sysmgr_regs->romcodegrp_ctrl, 81*4882a593Smuzhiyun SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); 82*4882a593Smuzhiyun else 83*4882a593Smuzhiyun clrbits_le32(&sysmgr_regs->romcodegrp_ctrl, 84*4882a593Smuzhiyun SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); 85*4882a593Smuzhiyun } 86