1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/pl310.h>
10 #include <asm/u-boot.h>
11 #include <asm/utils.h>
12 #include <image.h>
13 #include <asm/arch/reset_manager.h>
14 #include <spl.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/freeze_controller.h>
17 #include <asm/arch/clock_manager.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
20 #include <asm/arch/scu.h>
21 #include <asm/arch/nic301.h>
22 #include <asm/sections.h>
23 #include <fdtdec.h>
24 #include <watchdog.h>
25 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
26 #include <asm/arch/pinmux.h>
27 #endif
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
32 static struct pl310_regs *const pl310 =
33 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
34 static struct scu_registers *scu_regs =
35 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
36 static struct nic301_registers *nic301_regs =
37 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
38 #endif
39
40 static const struct socfpga_system_manager *sysmgr_regs =
41 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
42
spl_boot_device(void)43 u32 spl_boot_device(void)
44 {
45 const u32 bsel = readl(&sysmgr_regs->bootinfo);
46
47 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
48 case 0x1: /* FPGA (HPS2FPGA Bridge) */
49 return BOOT_DEVICE_RAM;
50 case 0x2: /* NAND Flash (1.8V) */
51 case 0x3: /* NAND Flash (3.0V) */
52 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
53 return BOOT_DEVICE_NAND;
54 case 0x4: /* SD/MMC External Transceiver (1.8V) */
55 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
56 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
57 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
58 return BOOT_DEVICE_MMC1;
59 case 0x6: /* QSPI Flash (1.8V) */
60 case 0x7: /* QSPI Flash (3.0V) */
61 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
62 return BOOT_DEVICE_SPI;
63 default:
64 printf("Invalid boot device (bsel=%08x)!\n", bsel);
65 hang();
66 }
67 }
68
69 #ifdef CONFIG_SPL_MMC_SUPPORT
spl_boot_mode(const u32 boot_device)70 u32 spl_boot_mode(const u32 boot_device)
71 {
72 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
73 return MMCSD_MODE_FS;
74 #else
75 return MMCSD_MODE_RAW;
76 #endif
77 }
78 #endif
79
80 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
socfpga_nic301_slave_ns(void)81 static void socfpga_nic301_slave_ns(void)
82 {
83 writel(0x1, &nic301_regs->lwhps2fpgaregs);
84 writel(0x1, &nic301_regs->hps2fpgaregs);
85 writel(0x1, &nic301_regs->acp);
86 writel(0x1, &nic301_regs->rom);
87 writel(0x1, &nic301_regs->ocram);
88 writel(0x1, &nic301_regs->sdrdata);
89 }
90
board_init_f(ulong dummy)91 void board_init_f(ulong dummy)
92 {
93 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
94 const struct cm_config *cm_default_cfg = cm_get_default_config();
95 #endif
96 unsigned long sdram_size;
97 unsigned long reg;
98
99 /*
100 * First C code to run. Clear fake OCRAM ECC first as SBE
101 * and DBE might triggered during power on
102 */
103 reg = readl(&sysmgr_regs->eccgrp_ocram);
104 if (reg & SYSMGR_ECC_OCRAM_SERR)
105 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
106 &sysmgr_regs->eccgrp_ocram);
107 if (reg & SYSMGR_ECC_OCRAM_DERR)
108 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
109 &sysmgr_regs->eccgrp_ocram);
110
111 memset(__bss_start, 0, __bss_end - __bss_start);
112
113 socfpga_nic301_slave_ns();
114
115 /* Configure ARM MPU SNSAC register. */
116 setbits_le32(&scu_regs->sacr, 0xfff);
117
118 /* Remap SDRAM to 0x0 */
119 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
120 writel(0x1, &pl310->pl310_addr_filter_start);
121
122 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
123 debug("Freezing all I/O banks\n");
124 /* freeze all IO banks */
125 sys_mgr_frzctrl_freeze_req();
126
127 /* Put everything into reset but L4WD0. */
128 socfpga_per_reset_all();
129 /* Put FPGA bridges into reset too. */
130 socfpga_bridges_reset(1);
131
132 socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
133 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
134 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
135
136 timer_init();
137
138 debug("Reconfigure Clock Manager\n");
139 /* reconfigure the PLLs */
140 if (cm_basic_init(cm_default_cfg))
141 hang();
142
143 /* Enable bootrom to configure IOs. */
144 sysmgr_config_warmrstcfgio(1);
145
146 /* configure the IOCSR / IO buffer settings */
147 if (scan_mgr_configure_iocsr())
148 hang();
149
150 sysmgr_config_warmrstcfgio(0);
151
152 /* configure the pin muxing through system manager */
153 sysmgr_config_warmrstcfgio(1);
154 sysmgr_pinmux_init();
155 sysmgr_config_warmrstcfgio(0);
156
157 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
158
159 /* De-assert reset for peripherals and bridges based on handoff */
160 reset_deassert_peripherals_handoff();
161 socfpga_bridges_reset(0);
162
163 debug("Unfreezing/Thaw all I/O banks\n");
164 /* unfreeze / thaw all IO banks */
165 sys_mgr_frzctrl_thaw_req();
166
167 /* enable console uart printing */
168 preloader_console_init();
169
170 if (sdram_mmr_init_full(0xffffffff) != 0) {
171 puts("SDRAM init failed.\n");
172 hang();
173 }
174
175 debug("SDRAM: Calibrating PHY\n");
176 /* SDRAM calibration */
177 if (sdram_calibration_full() == 0) {
178 puts("SDRAM calibration failed.\n");
179 hang();
180 }
181
182 sdram_size = sdram_calculate_size();
183 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
184
185 /* Sanity check ensure correct SDRAM size specified */
186 if (get_ram_size(0, sdram_size) != sdram_size) {
187 puts("SDRAM size check failed!\n");
188 hang();
189 }
190
191 socfpga_bridges_reset(1);
192
193 /* Configure simple malloc base pointer into RAM. */
194 gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
195 }
196 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
spl_board_init(void)197 void spl_board_init(void)
198 {
199 /* configuring the clock based on handoff */
200 cm_basic_init(gd->fdt_blob);
201 WATCHDOG_RESET();
202
203 config_dedicated_pins(gd->fdt_blob);
204 WATCHDOG_RESET();
205
206 /* Release UART from reset */
207 socfpga_reset_uart(0);
208
209 /* enable console uart printing */
210 preloader_console_init();
211 }
212
board_init_f(ulong dummy)213 void board_init_f(ulong dummy)
214 {
215 /*
216 * Configure Clock Manager to use intosc clock instead external osc to
217 * ensure success watchdog operation. We do it as early as possible.
218 */
219 cm_use_intosc();
220
221 socfpga_watchdog_disable();
222
223 arch_early_init_r();
224
225 #ifdef CONFIG_HW_WATCHDOG
226 /* release osc1 watchdog timer 0 from reset */
227 socfpga_reset_deassert_osc1wd0();
228
229 /* reconfigure and enable the watchdog */
230 hw_watchdog_init();
231 WATCHDOG_RESET();
232 #endif /* CONFIG_HW_WATCHDOG */
233 }
234 #endif
235