1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/arch/reset_manager.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun static const struct socfpga_reset_manager *reset_manager_base = 15*4882a593Smuzhiyun (void *)SOCFPGA_RSTMGR_ADDRESS; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Write the reset manager register to cause reset 19*4882a593Smuzhiyun */ reset_cpu(ulong addr)20*4882a593Smuzhiyunvoid reset_cpu(ulong addr) 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun /* request a warm reset */ 23*4882a593Smuzhiyun writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, 24*4882a593Smuzhiyun &reset_manager_base->ctrl); 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * infinite loop here as watchdog will trigger and reset 27*4882a593Smuzhiyun * the processor 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun while (1) 30*4882a593Smuzhiyun ; 31*4882a593Smuzhiyun } 32