1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <fdtdec.h>
11*4882a593Smuzhiyun
do_pinctr_pin(const void * blob,int child,const char * node_name)12*4882a593Smuzhiyun static int do_pinctr_pin(const void *blob, int child, const char *node_name)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun int len;
15*4882a593Smuzhiyun fdt_addr_t base_addr;
16*4882a593Smuzhiyun fdt_size_t size;
17*4882a593Smuzhiyun const u32 *cell;
18*4882a593Smuzhiyun u32 offset, value;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
21*4882a593Smuzhiyun if (base_addr != FDT_ADDR_T_NONE) {
22*4882a593Smuzhiyun cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len);
23*4882a593Smuzhiyun if (!cell || len <= 0)
24*4882a593Smuzhiyun return -EFAULT;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun debug("%p %d\n", cell, len);
27*4882a593Smuzhiyun for (; len > 0; len -= (2 * sizeof(u32))) {
28*4882a593Smuzhiyun offset = fdt32_to_cpu(*cell++);
29*4882a593Smuzhiyun value = fdt32_to_cpu(*cell++);
30*4882a593Smuzhiyun debug("<0x%x 0x%x>\n", offset, value);
31*4882a593Smuzhiyun writel(value, base_addr + offset);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun return -EFAULT;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
do_pinctrl_pins(const void * blob,int node,const char * child_name)38*4882a593Smuzhiyun static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun int child, len;
41*4882a593Smuzhiyun const char *node_name;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun child = fdt_first_subnode(blob, node);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (child < 0)
46*4882a593Smuzhiyun return -EINVAL;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun node_name = fdt_get_name(blob, child, &len);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun while (node_name) {
51*4882a593Smuzhiyun if (!strcmp(child_name, node_name))
52*4882a593Smuzhiyun return do_pinctr_pin(blob, child, node_name);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun child = fdt_next_subnode(blob, child);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (child < 0)
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun node_name = fdt_get_name(blob, child, &len);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return -EFAULT;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
config_dedicated_pins(const void * blob)65*4882a593Smuzhiyun int config_dedicated_pins(const void *blob)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun int node;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun node = fdtdec_next_compatible(blob, 0,
70*4882a593Smuzhiyun COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
71*4882a593Smuzhiyun if (node < 0)
72*4882a593Smuzhiyun return -EINVAL;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
75*4882a593Smuzhiyun return -EFAULT;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (do_pinctrl_pins(blob, node, "dedicated"))
78*4882a593Smuzhiyun return -EFAULT;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
config_pins(const void * blob,const char * pin_grp)83*4882a593Smuzhiyun int config_pins(const void *blob, const char *pin_grp)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun int node;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun node = fdtdec_next_compatible(blob, 0,
88*4882a593Smuzhiyun COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
89*4882a593Smuzhiyun if (node < 0)
90*4882a593Smuzhiyun return -EINVAL;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (do_pinctrl_pins(blob, node, pin_grp))
93*4882a593Smuzhiyun return -EFAULT;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97