1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _SYSTEM_MANAGER_H_ 8*4882a593Smuzhiyun #define _SYSTEM_MANAGER_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) 11*4882a593Smuzhiyun #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) 12*4882a593Smuzhiyun #define SYSMGR_ECC_OCRAM_EN BIT(0) 13*4882a593Smuzhiyun #define SYSMGR_ECC_OCRAM_SERR BIT(3) 14*4882a593Smuzhiyun #define SYSMGR_ECC_OCRAM_DERR BIT(4) 15*4882a593Smuzhiyun #define SYSMGR_FPGAINTF_USEFPGA 0x1 16*4882a593Smuzhiyun #define SYSMGR_FPGAINTF_SPIM0 BIT(0) 17*4882a593Smuzhiyun #define SYSMGR_FPGAINTF_SPIM1 BIT(1) 18*4882a593Smuzhiyun #define SYSMGR_FPGAINTF_EMAC0 BIT(2) 19*4882a593Smuzhiyun #define SYSMGR_FPGAINTF_EMAC1 BIT(3) 20*4882a593Smuzhiyun #define SYSMGR_FPGAINTF_NAND BIT(4) 21*4882a593Smuzhiyun #define SYSMGR_FPGAINTF_SDMMC BIT(5) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* EMAC Group Bit definitions */ 26*4882a593Smuzhiyun #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 27*4882a593Smuzhiyun #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 28*4882a593Smuzhiyun #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 31*4882a593Smuzhiyun #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 32*4882a593Smuzhiyun #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* For dedicated IO configuration */ 35*4882a593Smuzhiyun /* Voltage select enums */ 36*4882a593Smuzhiyun #define VOLTAGE_SEL_3V 0x0 37*4882a593Smuzhiyun #define VOLTAGE_SEL_1P8V 0x1 38*4882a593Smuzhiyun #define VOLTAGE_SEL_2P5V 0x2 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Input buffer enable */ 41*4882a593Smuzhiyun #define INPUT_BUF_DISABLE 0 42*4882a593Smuzhiyun #define INPUT_BUF_1P8V 1 43*4882a593Smuzhiyun #define INPUT_BUF_2P5V3V 2 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Weak pull up enable */ 46*4882a593Smuzhiyun #define WK_PU_DISABLE 0 47*4882a593Smuzhiyun #define WK_PU_ENABLE 1 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Pull up slew rate control */ 50*4882a593Smuzhiyun #define PU_SLW_RT_SLOW 0 51*4882a593Smuzhiyun #define PU_SLW_RT_FAST 1 52*4882a593Smuzhiyun #define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Pull down slew rate control */ 55*4882a593Smuzhiyun #define PD_SLW_RT_SLOW 0 56*4882a593Smuzhiyun #define PD_SLW_RT_FAST 1 57*4882a593Smuzhiyun #define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Drive strength control */ 60*4882a593Smuzhiyun #define PU_DRV_STRG_DEFAULT 0x10 61*4882a593Smuzhiyun #define PD_DRV_STRG_DEFAULT 0x10 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* bit position */ 64*4882a593Smuzhiyun #define PD_DRV_STRG_LSB 0 65*4882a593Smuzhiyun #define PD_SLW_RT_LSB 5 66*4882a593Smuzhiyun #define PU_DRV_STRG_LSB 8 67*4882a593Smuzhiyun #define PU_SLW_RT_LSB 13 68*4882a593Smuzhiyun #define WK_PU_LSB 16 69*4882a593Smuzhiyun #define INPUT_BUF_LSB 17 70*4882a593Smuzhiyun #define BIAS_TRIM_LSB 19 71*4882a593Smuzhiyun #define VOLTAGE_SEL_LSB 0 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0) 74*4882a593Smuzhiyun #define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4) 75*4882a593Smuzhiyun #define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8) 76*4882a593Smuzhiyun #define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16) 77*4882a593Smuzhiyun #define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20) 78*4882a593Smuzhiyun #define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24) 79*4882a593Smuzhiyun #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1) 82*4882a593Smuzhiyun #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 85*4882a593Smuzhiyun #include <asm/arch/system_manager_gen5.h> 86*4882a593Smuzhiyun #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 87*4882a593Smuzhiyun #include <asm/arch/system_manager_arria10.h> 88*4882a593Smuzhiyun #endif 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \ 91*4882a593Smuzhiyun (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* _SYSTEM_MANAGER_H_ */ 94