1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: BSD-3-Clause 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _FPGA_MANAGER_H_ 9*4882a593Smuzhiyun #define _FPGA_MANAGER_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <altera.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 14*4882a593Smuzhiyun #include <asm/arch/fpga_manager_gen5.h> 15*4882a593Smuzhiyun #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 16*4882a593Smuzhiyun #include <asm/arch/fpga_manager_arria10.h> 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* FPGA CD Ratio Value */ 20*4882a593Smuzhiyun #define CDRATIO_x1 0x0 21*4882a593Smuzhiyun #define CDRATIO_x2 0x1 22*4882a593Smuzhiyun #define CDRATIO_x4 0x2 23*4882a593Smuzhiyun #define CDRATIO_x8 0x3 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Common prototypes */ 28*4882a593Smuzhiyun int fpgamgr_get_mode(void); 29*4882a593Smuzhiyun int fpgamgr_poll_fpga_ready(void); 30*4882a593Smuzhiyun void fpgamgr_program_write(const void *rbf_data, size_t rbf_size); 31*4882a593Smuzhiyun int fpgamgr_test_fpga_ready(void); 32*4882a593Smuzhiyun int fpgamgr_dclkcnt_set(unsigned long cnt); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 35*4882a593Smuzhiyun #endif /* _FPGA_MANAGER_H_ */ 36