1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CLOCK_MANAGER_H_ 8*4882a593Smuzhiyun #define _CLOCK_MANAGER_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASSEMBLER__ 11*4882a593Smuzhiyun void cm_wait_for_lock(u32 mask); 12*4882a593Smuzhiyun int cm_wait_for_fsm(void); 13*4882a593Smuzhiyun void cm_print_clock_quick_summary(void); 14*4882a593Smuzhiyun #endif 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 17*4882a593Smuzhiyun #include <asm/arch/clock_manager_gen5.h> 18*4882a593Smuzhiyun #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 19*4882a593Smuzhiyun #include <asm/arch/clock_manager_arria10.h> 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* _CLOCK_MANAGER_H_ */ 23