1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Specialty padding for the Altera SoCFPGA preloader image 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __BOOT0_H 8*4882a593Smuzhiyun #define __BOOT0_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun _start: 11*4882a593Smuzhiyun ARM_VECTORS 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 14*4882a593Smuzhiyun .balignl 64,0xf33db33f; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun .word 0x1337c0d3; /* SoCFPGA preloader validation word */ 17*4882a593Smuzhiyun .word 0xc01df00d; /* Version, flags, length */ 18*4882a593Smuzhiyun .word 0xcafec0d3; /* Checksum, zero-pad */ 19*4882a593Smuzhiyun nop; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun b reset; /* SoCFPGA jumps here */ 22*4882a593Smuzhiyun nop; 23*4882a593Smuzhiyun nop; 24*4882a593Smuzhiyun nop; 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #endif /* __BOOT0_H */ 28