1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Altera Corporation <www.altera.com> 3*4882a593Smuzhiyun * All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This file contains only support functions used also by the SoCFPGA 6*4882a593Smuzhiyun * platform code, the real meat is located in drivers/fpga/socfpga.c . 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: BSD-3-Clause 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun #include <linux/errno.h> 14*4882a593Smuzhiyun #include <asm/arch/fpga_manager.h> 15*4882a593Smuzhiyun #include <asm/arch/reset_manager.h> 16*4882a593Smuzhiyun #include <asm/arch/system_manager.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Timeout count */ 21*4882a593Smuzhiyun #define FPGA_TIMEOUT_CNT 0x1000000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun static struct socfpga_fpga_manager *fpgamgr_regs = 24*4882a593Smuzhiyun (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Check whether FPGA Init_Done signal is high */ is_fpgamgr_initdone_high(void)27*4882a593Smuzhiyunstatic int is_fpgamgr_initdone_high(void) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun unsigned long val; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun val = readl(&fpgamgr_regs->gpio_ext_porta); 32*4882a593Smuzhiyun return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; 33*4882a593Smuzhiyun } 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Get the FPGA mode */ fpgamgr_get_mode(void)36*4882a593Smuzhiyunint fpgamgr_get_mode(void) 37*4882a593Smuzhiyun { 38*4882a593Smuzhiyun unsigned long val; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun val = readl(&fpgamgr_regs->stat); 41*4882a593Smuzhiyun return val & FPGAMGRREGS_STAT_MODE_MASK; 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Check whether FPGA is ready to be accessed */ fpgamgr_test_fpga_ready(void)45*4882a593Smuzhiyunint fpgamgr_test_fpga_ready(void) 46*4882a593Smuzhiyun { 47*4882a593Smuzhiyun /* Check for init done signal */ 48*4882a593Smuzhiyun if (!is_fpgamgr_initdone_high()) 49*4882a593Smuzhiyun return 0; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Check again to avoid false glitches */ 52*4882a593Smuzhiyun if (!is_fpgamgr_initdone_high()) 53*4882a593Smuzhiyun return 0; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) 56*4882a593Smuzhiyun return 0; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun return 1; 59*4882a593Smuzhiyun } 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Poll until FPGA is ready to be accessed or timeout occurred */ fpgamgr_poll_fpga_ready(void)62*4882a593Smuzhiyunint fpgamgr_poll_fpga_ready(void) 63*4882a593Smuzhiyun { 64*4882a593Smuzhiyun unsigned long i; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* If FPGA is blank, wait till WD invoke warm reset */ 67*4882a593Smuzhiyun for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { 68*4882a593Smuzhiyun /* check for init done signal */ 69*4882a593Smuzhiyun if (!is_fpgamgr_initdone_high()) 70*4882a593Smuzhiyun continue; 71*4882a593Smuzhiyun /* check again to avoid false glitches */ 72*4882a593Smuzhiyun if (!is_fpgamgr_initdone_high()) 73*4882a593Smuzhiyun continue; 74*4882a593Smuzhiyun return 1; 75*4882a593Smuzhiyun } 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun return 0; 78*4882a593Smuzhiyun } 79