1 /*
2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock_manager.h>
10 #include <wait_bit.h>
11
12 DECLARE_GLOBAL_DATA_PTR;
13
14 static const struct socfpga_clock_manager *clock_manager_base =
15 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
16
17 /*
18 * function to write the bypass register which requires a poll of the
19 * busy bit
20 */
cm_write_bypass(u32 val)21 static void cm_write_bypass(u32 val)
22 {
23 writel(val, &clock_manager_base->bypass);
24 cm_wait_for_fsm();
25 }
26
27 /* function to write the ctrl register which requires a poll of the busy bit */
cm_write_ctrl(u32 val)28 static void cm_write_ctrl(u32 val)
29 {
30 writel(val, &clock_manager_base->ctrl);
31 cm_wait_for_fsm();
32 }
33
34 /* function to write a clock register that has phase information */
cm_write_with_phase(u32 value,u32 reg_address,u32 mask)35 static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
36 {
37 int ret;
38
39 /* poll until phase is zero */
40 ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
41 if (ret)
42 return ret;
43
44 writel(value, reg_address);
45
46 return wait_for_bit_le32(reg_address, mask, false, 20000, false);
47 }
48
49 /*
50 * Setup clocks while making no assumptions about previous state of the clocks.
51 *
52 * Start by being paranoid and gate all sw managed clocks
53 * Put all plls in bypass
54 * Put all plls VCO registers back to reset value (bandgap power down).
55 * Put peripheral and main pll src to reset value to avoid glitch.
56 * Delay 5 us.
57 * Deassert bandgap power down and set numerator and denominator
58 * Start 7 us timer.
59 * set internal dividers
60 * Wait for 7 us timer.
61 * Enable plls
62 * Set external dividers while plls are locking
63 * Wait for pll lock
64 * Assert/deassert outreset all.
65 * Take all pll's out of bypass
66 * Clear safe mode
67 * set source main and peripheral clocks
68 * Ungate clocks
69 */
70
cm_basic_init(const struct cm_config * const cfg)71 int cm_basic_init(const struct cm_config * const cfg)
72 {
73 unsigned long end;
74 int ret;
75
76 /* Start by being paranoid and gate all sw managed clocks */
77
78 /*
79 * We need to disable nandclk
80 * and then do another apb access before disabling
81 * gatting off the rest of the periperal clocks.
82 */
83 writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
84 readl(&clock_manager_base->per_pll.en),
85 &clock_manager_base->per_pll.en);
86
87 /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
88 writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
89 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
90 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
91 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
92 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
93 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
94 &clock_manager_base->main_pll.en);
95
96 writel(0, &clock_manager_base->sdr_pll.en);
97
98 /* now we can gate off the rest of the peripheral clocks */
99 writel(0, &clock_manager_base->per_pll.en);
100
101 /* Put all plls in bypass */
102 cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
103 CLKMGR_BYPASS_MAINPLL);
104
105 /* Put all plls VCO registers back to reset value. */
106 writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
107 ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
108 &clock_manager_base->main_pll.vco);
109 writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
110 ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
111 &clock_manager_base->per_pll.vco);
112 writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
113 ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
114 &clock_manager_base->sdr_pll.vco);
115
116 /*
117 * The clocks to the flash devices and the L4_MAIN clocks can
118 * glitch when coming out of safe mode if their source values
119 * are different from their reset value. So the trick it to
120 * put them back to their reset state, and change input
121 * after exiting safe mode but before ungating the clocks.
122 */
123 writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
124 &clock_manager_base->per_pll.src);
125 writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
126 &clock_manager_base->main_pll.l4src);
127
128 /* read back for the required 5 us delay. */
129 readl(&clock_manager_base->main_pll.vco);
130 readl(&clock_manager_base->per_pll.vco);
131 readl(&clock_manager_base->sdr_pll.vco);
132
133
134 /*
135 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
136 * with numerator and denominator.
137 */
138 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
139 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
140 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
141
142 /*
143 * Time starts here. Must wait 7 us from
144 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
145 */
146 end = timer_get_us() + 7;
147
148 /* main mpu */
149 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
150
151 /* altera group mpuclk */
152 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
153
154 /* main main clock */
155 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
156
157 /* main for dbg */
158 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
159
160 /* main for cfgs2fuser0clk */
161 writel(cfg->cfg2fuser0clk,
162 &clock_manager_base->main_pll.cfgs2fuser0clk);
163
164 /* Peri emac0 50 MHz default to RMII */
165 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
166
167 /* Peri emac1 50 MHz default to RMII */
168 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
169
170 /* Peri QSPI */
171 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
172
173 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
174
175 /* Peri pernandsdmmcclk */
176 writel(cfg->mainnandsdmmcclk,
177 &clock_manager_base->main_pll.mainnandsdmmcclk);
178
179 writel(cfg->pernandsdmmcclk,
180 &clock_manager_base->per_pll.pernandsdmmcclk);
181
182 /* Peri perbaseclk */
183 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
184
185 /* Peri s2fuser1clk */
186 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
187
188 /* 7 us must have elapsed before we can enable the VCO */
189 while (timer_get_us() < end)
190 ;
191
192 /* Enable vco */
193 /* main pll vco */
194 writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
195 &clock_manager_base->main_pll.vco);
196
197 /* periferal pll */
198 writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
199 &clock_manager_base->per_pll.vco);
200
201 /* sdram pll vco */
202 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
203 &clock_manager_base->sdr_pll.vco);
204
205 /* L3 MP and L3 SP */
206 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
207
208 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
209
210 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
211
212 /* L4 MP, L4 SP, can0, and can1 */
213 writel(cfg->perdiv, &clock_manager_base->per_pll.div);
214
215 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
216
217 cm_wait_for_lock(LOCKED_MASK);
218
219 /* write the sdram clock counters before toggling outreset all */
220 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
221 &clock_manager_base->sdr_pll.ddrdqsclk);
222
223 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
224 &clock_manager_base->sdr_pll.ddr2xdqsclk);
225
226 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
227 &clock_manager_base->sdr_pll.ddrdqclk);
228
229 writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
230 &clock_manager_base->sdr_pll.s2fuser2clk);
231
232 /*
233 * after locking, but before taking out of bypass
234 * assert/deassert outresetall
235 */
236 u32 mainvco = readl(&clock_manager_base->main_pll.vco);
237
238 /* assert main outresetall */
239 writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
240 &clock_manager_base->main_pll.vco);
241
242 u32 periphvco = readl(&clock_manager_base->per_pll.vco);
243
244 /* assert pheriph outresetall */
245 writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
246 &clock_manager_base->per_pll.vco);
247
248 /* assert sdram outresetall */
249 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
250 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
251 &clock_manager_base->sdr_pll.vco);
252
253 /* deassert main outresetall */
254 writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
255 &clock_manager_base->main_pll.vco);
256
257 /* deassert pheriph outresetall */
258 writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
259 &clock_manager_base->per_pll.vco);
260
261 /* deassert sdram outresetall */
262 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
263 &clock_manager_base->sdr_pll.vco);
264
265 /*
266 * now that we've toggled outreset all, all the clocks
267 * are aligned nicely; so we can change any phase.
268 */
269 ret = cm_write_with_phase(cfg->ddrdqsclk,
270 (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
271 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
272 if (ret)
273 return ret;
274
275 /* SDRAM DDR2XDQSCLK */
276 ret = cm_write_with_phase(cfg->ddr2xdqsclk,
277 (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
278 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
279 if (ret)
280 return ret;
281
282 ret = cm_write_with_phase(cfg->ddrdqclk,
283 (u32)&clock_manager_base->sdr_pll.ddrdqclk,
284 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
285 if (ret)
286 return ret;
287
288 ret = cm_write_with_phase(cfg->s2fuser2clk,
289 (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
290 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
291 if (ret)
292 return ret;
293
294 /* Take all three PLLs out of bypass when safe mode is cleared. */
295 cm_write_bypass(0);
296
297 /* clear safe mode */
298 cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
299
300 /*
301 * now that safe mode is clear with clocks gated
302 * it safe to change the source mux for the flashes the the L4_MAIN
303 */
304 writel(cfg->persrc, &clock_manager_base->per_pll.src);
305 writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
306
307 /* Now ungate non-hw-managed clocks */
308 writel(~0, &clock_manager_base->main_pll.en);
309 writel(~0, &clock_manager_base->per_pll.en);
310 writel(~0, &clock_manager_base->sdr_pll.en);
311
312 /* Clear the loss of lock bits (write 1 to clear) */
313 writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
314 CLKMGR_INTER_MAINPLLLOST_MASK,
315 &clock_manager_base->inter);
316
317 return 0;
318 }
319
cm_get_main_vco_clk_hz(void)320 static unsigned int cm_get_main_vco_clk_hz(void)
321 {
322 u32 reg, clock;
323
324 /* get the main VCO clock */
325 reg = readl(&clock_manager_base->main_pll.vco);
326 clock = cm_get_osc_clk_hz(1);
327 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
328 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
329 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
330 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
331
332 return clock;
333 }
334
cm_get_per_vco_clk_hz(void)335 static unsigned int cm_get_per_vco_clk_hz(void)
336 {
337 u32 reg, clock = 0;
338
339 /* identify PER PLL clock source */
340 reg = readl(&clock_manager_base->per_pll.vco);
341 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
342 CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
343 if (reg == CLKMGR_VCO_SSRC_EOSC1)
344 clock = cm_get_osc_clk_hz(1);
345 else if (reg == CLKMGR_VCO_SSRC_EOSC2)
346 clock = cm_get_osc_clk_hz(2);
347 else if (reg == CLKMGR_VCO_SSRC_F2S)
348 clock = cm_get_f2s_per_ref_clk_hz();
349
350 /* get the PER VCO clock */
351 reg = readl(&clock_manager_base->per_pll.vco);
352 clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
353 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
354 clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
355 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
356
357 return clock;
358 }
359
cm_get_mpu_clk_hz(void)360 unsigned long cm_get_mpu_clk_hz(void)
361 {
362 u32 reg, clock;
363
364 clock = cm_get_main_vco_clk_hz();
365
366 /* get the MPU clock */
367 reg = readl(&clock_manager_base->altera.mpuclk);
368 clock /= (reg + 1);
369 reg = readl(&clock_manager_base->main_pll.mpuclk);
370 clock /= (reg + 1);
371 return clock;
372 }
373
cm_get_sdram_clk_hz(void)374 unsigned long cm_get_sdram_clk_hz(void)
375 {
376 u32 reg, clock = 0;
377
378 /* identify SDRAM PLL clock source */
379 reg = readl(&clock_manager_base->sdr_pll.vco);
380 reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
381 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
382 if (reg == CLKMGR_VCO_SSRC_EOSC1)
383 clock = cm_get_osc_clk_hz(1);
384 else if (reg == CLKMGR_VCO_SSRC_EOSC2)
385 clock = cm_get_osc_clk_hz(2);
386 else if (reg == CLKMGR_VCO_SSRC_F2S)
387 clock = cm_get_f2s_sdr_ref_clk_hz();
388
389 /* get the SDRAM VCO clock */
390 reg = readl(&clock_manager_base->sdr_pll.vco);
391 clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
392 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
393 clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
394 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
395
396 /* get the SDRAM (DDR_DQS) clock */
397 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
398 reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
399 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
400 clock /= (reg + 1);
401
402 return clock;
403 }
404
cm_get_l4_sp_clk_hz(void)405 unsigned int cm_get_l4_sp_clk_hz(void)
406 {
407 u32 reg, clock = 0;
408
409 /* identify the source of L4 SP clock */
410 reg = readl(&clock_manager_base->main_pll.l4src);
411 reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
412 CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
413
414 if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
415 clock = cm_get_main_vco_clk_hz();
416
417 /* get the clock prior L4 SP divider (main clk) */
418 reg = readl(&clock_manager_base->altera.mainclk);
419 clock /= (reg + 1);
420 reg = readl(&clock_manager_base->main_pll.mainclk);
421 clock /= (reg + 1);
422 } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
423 clock = cm_get_per_vco_clk_hz();
424
425 /* get the clock prior L4 SP divider (periph_base_clk) */
426 reg = readl(&clock_manager_base->per_pll.perbaseclk);
427 clock /= (reg + 1);
428 }
429
430 /* get the L4 SP clock which supplied to UART */
431 reg = readl(&clock_manager_base->main_pll.maindiv);
432 reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
433 CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
434 clock = clock / (1 << reg);
435
436 return clock;
437 }
438
cm_get_mmc_controller_clk_hz(void)439 unsigned int cm_get_mmc_controller_clk_hz(void)
440 {
441 u32 reg, clock = 0;
442
443 /* identify the source of MMC clock */
444 reg = readl(&clock_manager_base->per_pll.src);
445 reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
446 CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
447
448 if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
449 clock = cm_get_f2s_per_ref_clk_hz();
450 } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
451 clock = cm_get_main_vco_clk_hz();
452
453 /* get the SDMMC clock */
454 reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
455 clock /= (reg + 1);
456 } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
457 clock = cm_get_per_vco_clk_hz();
458
459 /* get the SDMMC clock */
460 reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
461 clock /= (reg + 1);
462 }
463
464 /* further divide by 4 as we have fixed divider at wrapper */
465 clock /= 4;
466 return clock;
467 }
468
cm_get_qspi_controller_clk_hz(void)469 unsigned int cm_get_qspi_controller_clk_hz(void)
470 {
471 u32 reg, clock = 0;
472
473 /* identify the source of QSPI clock */
474 reg = readl(&clock_manager_base->per_pll.src);
475 reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
476 CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
477
478 if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
479 clock = cm_get_f2s_per_ref_clk_hz();
480 } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
481 clock = cm_get_main_vco_clk_hz();
482
483 /* get the qspi clock */
484 reg = readl(&clock_manager_base->main_pll.mainqspiclk);
485 clock /= (reg + 1);
486 } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
487 clock = cm_get_per_vco_clk_hz();
488
489 /* get the qspi clock */
490 reg = readl(&clock_manager_base->per_pll.perqspiclk);
491 clock /= (reg + 1);
492 }
493
494 return clock;
495 }
496
cm_get_spi_controller_clk_hz(void)497 unsigned int cm_get_spi_controller_clk_hz(void)
498 {
499 u32 reg, clock = 0;
500
501 clock = cm_get_per_vco_clk_hz();
502
503 /* get the clock prior L4 SP divider (periph_base_clk) */
504 reg = readl(&clock_manager_base->per_pll.perbaseclk);
505 clock /= (reg + 1);
506
507 return clock;
508 }
509
cm_print_clock_quick_summary(void)510 void cm_print_clock_quick_summary(void)
511 {
512 printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
513 printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
514 printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
515 printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
516 printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
517 printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
518 printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
519 printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
520 printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
521 printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
522 }
523