1*4882a593Smuzhiyunif ARCH_SOCFPGA 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig SPL_LIBCOMMON_SUPPORT 4*4882a593Smuzhiyun default y 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunconfig SPL_LIBDISK_SUPPORT 7*4882a593Smuzhiyun default y 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunconfig SPL_LIBGENERIC_SUPPORT 10*4882a593Smuzhiyun default y 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunconfig SPL_MMC_SUPPORT 13*4882a593Smuzhiyun default y if DM_MMC 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunconfig SPL_NAND_SUPPORT 16*4882a593Smuzhiyun default y if SPL_NAND_DENALI 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunconfig SPL_SERIAL_SUPPORT 19*4882a593Smuzhiyun default y 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunconfig SPL_SPI_FLASH_SUPPORT 22*4882a593Smuzhiyun default y if SPL_SPI_SUPPORT 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunconfig SPL_SPI_SUPPORT 25*4882a593Smuzhiyun default y if DM_SPI 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunconfig SPL_WATCHDOG_SUPPORT 28*4882a593Smuzhiyun default y 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunconfig SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE 31*4882a593Smuzhiyun default y 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunconfig SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 34*4882a593Smuzhiyun default 0xa2 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunconfig TARGET_SOCFPGA_ARRIA5 37*4882a593Smuzhiyun bool 38*4882a593Smuzhiyun select TARGET_SOCFPGA_GEN5 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunconfig TARGET_SOCFPGA_ARRIA10 41*4882a593Smuzhiyun bool 42*4882a593Smuzhiyun select SPL_BOARD_INIT if SPL 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunconfig TARGET_SOCFPGA_CYCLONE5 45*4882a593Smuzhiyun bool 46*4882a593Smuzhiyun select TARGET_SOCFPGA_GEN5 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunconfig TARGET_SOCFPGA_GEN5 49*4882a593Smuzhiyun bool 50*4882a593Smuzhiyun select ALTERA_SDRAM 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunchoice 53*4882a593Smuzhiyun prompt "Altera SOCFPGA board select" 54*4882a593Smuzhiyun optional 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunconfig TARGET_SOCFPGA_ARRIA10_SOCDK 57*4882a593Smuzhiyun bool "Altera SOCFPGA SoCDK (Arria 10)" 58*4882a593Smuzhiyun select TARGET_SOCFPGA_ARRIA10 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunconfig TARGET_SOCFPGA_ARRIA5_SOCDK 61*4882a593Smuzhiyun bool "Altera SOCFPGA SoCDK (Arria V)" 62*4882a593Smuzhiyun select TARGET_SOCFPGA_ARRIA5 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunconfig TARGET_SOCFPGA_CYCLONE5_SOCDK 65*4882a593Smuzhiyun bool "Altera SOCFPGA SoCDK (Cyclone V)" 66*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunconfig TARGET_SOCFPGA_ARIES_MCVEVK 69*4882a593Smuzhiyun bool "Aries MCVEVK (Cyclone V)" 70*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunconfig TARGET_SOCFPGA_EBV_SOCRATES 73*4882a593Smuzhiyun bool "EBV SoCrates (Cyclone V)" 74*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunconfig TARGET_SOCFPGA_IS1 77*4882a593Smuzhiyun bool "IS1 (Cyclone V)" 78*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 79*4882a593Smuzhiyun 80*4882a593Smuzhiyunconfig TARGET_SOCFPGA_SAMTEC_VINING_FPGA 81*4882a593Smuzhiyun bool "samtec VIN|ING FPGA (Cyclone V)" 82*4882a593Smuzhiyun select BOARD_LATE_INIT 83*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunconfig TARGET_SOCFPGA_SR1500 86*4882a593Smuzhiyun bool "SR1500 (Cyclone V)" 87*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 88*4882a593Smuzhiyun 89*4882a593Smuzhiyunconfig TARGET_SOCFPGA_TERASIC_DE0_NANO 90*4882a593Smuzhiyun bool "Terasic DE0-Nano-Atlas (Cyclone V)" 91*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunconfig TARGET_SOCFPGA_TERASIC_DE10_NANO 94*4882a593Smuzhiyun bool "Terasic DE10-Nano (Cyclone V)" 95*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 96*4882a593Smuzhiyun 97*4882a593Smuzhiyunconfig TARGET_SOCFPGA_TERASIC_DE1_SOC 98*4882a593Smuzhiyun bool "Terasic DE1-SoC (Cyclone V)" 99*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunconfig TARGET_SOCFPGA_TERASIC_SOCKIT 102*4882a593Smuzhiyun bool "Terasic SoCkit (Cyclone V)" 103*4882a593Smuzhiyun select TARGET_SOCFPGA_CYCLONE5 104*4882a593Smuzhiyun 105*4882a593Smuzhiyunendchoice 106*4882a593Smuzhiyun 107*4882a593Smuzhiyunconfig SYS_BOARD 108*4882a593Smuzhiyun default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 109*4882a593Smuzhiyun default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 110*4882a593Smuzhiyun default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 111*4882a593Smuzhiyun default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 112*4882a593Smuzhiyun default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 113*4882a593Smuzhiyun default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 114*4882a593Smuzhiyun default "is1" if TARGET_SOCFPGA_IS1 115*4882a593Smuzhiyun default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 116*4882a593Smuzhiyun default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 117*4882a593Smuzhiyun default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 118*4882a593Smuzhiyun default "sr1500" if TARGET_SOCFPGA_SR1500 119*4882a593Smuzhiyun default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 120*4882a593Smuzhiyun 121*4882a593Smuzhiyunconfig SYS_VENDOR 122*4882a593Smuzhiyun default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 123*4882a593Smuzhiyun default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 124*4882a593Smuzhiyun default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 125*4882a593Smuzhiyun default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK 126*4882a593Smuzhiyun default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 127*4882a593Smuzhiyun default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 128*4882a593Smuzhiyun default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 129*4882a593Smuzhiyun default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 130*4882a593Smuzhiyun default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 131*4882a593Smuzhiyun default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunconfig SYS_SOC 134*4882a593Smuzhiyun default "socfpga" 135*4882a593Smuzhiyun 136*4882a593Smuzhiyunconfig SYS_CONFIG_NAME 137*4882a593Smuzhiyun default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 138*4882a593Smuzhiyun default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 139*4882a593Smuzhiyun default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 140*4882a593Smuzhiyun default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 141*4882a593Smuzhiyun default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 142*4882a593Smuzhiyun default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 143*4882a593Smuzhiyun default "socfpga_is1" if TARGET_SOCFPGA_IS1 144*4882a593Smuzhiyun default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 145*4882a593Smuzhiyun default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 146*4882a593Smuzhiyun default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 147*4882a593Smuzhiyun default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 148*4882a593Smuzhiyun default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 149*4882a593Smuzhiyun 150*4882a593Smuzhiyunendif 151