1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 Samsung Electronics 3*4882a593Smuzhiyun * Naveen Krishna Ch <ch.naveen@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Note: This file contains the register description for Memory subsystem 8*4882a593Smuzhiyun * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Only SROMC is defined as of now 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __ASM_ARCH_SROMC_H_ 14*4882a593Smuzhiyun #define __ASM_ARCH_SROMC_H_ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) 17*4882a593Smuzhiyun #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ 18*4882a593Smuzhiyun /* 1-> Byte base address*/ 19*4882a593Smuzhiyun #define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) 20*4882a593Smuzhiyun #define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ 23*4882a593Smuzhiyun #define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ 24*4882a593Smuzhiyun #define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ 25*4882a593Smuzhiyun #define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ 26*4882a593Smuzhiyun #define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ 27*4882a593Smuzhiyun #define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ 28*4882a593Smuzhiyun #define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 31*4882a593Smuzhiyun struct s5p_sromc { 32*4882a593Smuzhiyun unsigned int bw; 33*4882a593Smuzhiyun unsigned int bc[6]; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ 38*4882a593Smuzhiyun void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __ASM_ARCH_SMC_H_ */ 41