1 /*
2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd
3 * Author: Zhihuan He <huan.he@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <ram.h>
10 #include <asm/arch/sdram.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/grf_rv1108.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #define GRF_BASE 0x10300000
17
board_debug_uart_init(void)18 void board_debug_uart_init(void)
19 {
20 #ifdef CONFIG_SPL_BUILD
21 struct rv1108_grf *grf = (void *)GRF_BASE;
22
23 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0x10230000)
24 enum {
25 GPIO3A6_SHIFT = 12,
26 GPIO3A6_MASK = 3 << GPIO3A6_SHIFT,
27 GPIO3A6_GPIO = 0,
28 GPIO3A6_UART1_SOUT,
29
30 GPIO3A5_SHIFT = 10,
31 GPIO3A5_MASK = 3 << GPIO3A5_SHIFT,
32 GPIO3A5_GPIO = 0,
33 GPIO3A5_UART1_SIN,
34 };
35
36 rk_clrsetreg(&grf->gpio3a_iomux, /* UART0 */
37 GPIO3A6_MASK | GPIO3A5_MASK,
38 GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
39 GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
40 #else
41 enum {
42 GPIO2D2_SHIFT = 4,
43 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
44 GPIO2D2_GPIO = 0,
45 GPIO2D2_UART2_SOUT_M0,
46
47 GPIO2D1_SHIFT = 2,
48 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
49 GPIO2D1_GPIO = 0,
50 GPIO2D1_UART2_SIN_M0,
51 };
52
53 rk_clrsetreg(&grf->gpio2d_iomux, /* UART2 */
54 GPIO2D2_MASK | GPIO2D1_MASK,
55 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
56 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
57 #endif
58 #endif /*CONFIG_SPL_BUILD*/
59 }
60