1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2018 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun * Author: Zhihuan He <huan.he@rock-chips.com>
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <ram.h>
10*4882a593Smuzhiyun #include <asm/arch/sdram.h>
11*4882a593Smuzhiyun #include <asm/arch/hardware.h>
12*4882a593Smuzhiyun #include <asm/arch/grf_rv1108.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define GRF_BASE 0x10300000
17*4882a593Smuzhiyun
board_debug_uart_init(void)18*4882a593Smuzhiyun void board_debug_uart_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
21*4882a593Smuzhiyun struct rv1108_grf *grf = (void *)GRF_BASE;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0x10230000)
24*4882a593Smuzhiyun enum {
25*4882a593Smuzhiyun GPIO3A6_SHIFT = 12,
26*4882a593Smuzhiyun GPIO3A6_MASK = 3 << GPIO3A6_SHIFT,
27*4882a593Smuzhiyun GPIO3A6_GPIO = 0,
28*4882a593Smuzhiyun GPIO3A6_UART1_SOUT,
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun GPIO3A5_SHIFT = 10,
31*4882a593Smuzhiyun GPIO3A5_MASK = 3 << GPIO3A5_SHIFT,
32*4882a593Smuzhiyun GPIO3A5_GPIO = 0,
33*4882a593Smuzhiyun GPIO3A5_UART1_SIN,
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun rk_clrsetreg(&grf->gpio3a_iomux, /* UART0 */
37*4882a593Smuzhiyun GPIO3A6_MASK | GPIO3A5_MASK,
38*4882a593Smuzhiyun GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
39*4882a593Smuzhiyun GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
40*4882a593Smuzhiyun #else
41*4882a593Smuzhiyun enum {
42*4882a593Smuzhiyun GPIO2D2_SHIFT = 4,
43*4882a593Smuzhiyun GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
44*4882a593Smuzhiyun GPIO2D2_GPIO = 0,
45*4882a593Smuzhiyun GPIO2D2_UART2_SOUT_M0,
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun GPIO2D1_SHIFT = 2,
48*4882a593Smuzhiyun GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
49*4882a593Smuzhiyun GPIO2D1_GPIO = 0,
50*4882a593Smuzhiyun GPIO2D1_UART2_SIN_M0,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun rk_clrsetreg(&grf->gpio2d_iomux, /* UART2 */
54*4882a593Smuzhiyun GPIO2D2_MASK | GPIO2D1_MASK,
55*4882a593Smuzhiyun GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
56*4882a593Smuzhiyun GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun #endif /*CONFIG_SPL_BUILD*/
59*4882a593Smuzhiyun }
60