1 /*
2 * Copyright (c) 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/grf_rk3568.h>
13 #include <asm/arch/rk_atags.h>
14 #include <linux/libfdt.h>
15 #include <fdt_support.h>
16 #include <asm/arch/clock.h>
17 #include <dt-bindings/clock/rk3568-cru.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define PMUGRF_BASE 0xfdc20000
22 #define GRF_BASE 0xfdc60000
23 #define GRF_GPIO1B_IOMUX_H 0x0C
24 #define GRF_GPIO1C_IOMUX_L 0x10
25 #define GRF_GPIO1C_IOMUX_H 0x14
26 #define GRF_GPIO1D_IOMUX_L 0x18
27 #define GRF_GPIO1D_IOMUX_H 0x1C
28 #define GRF_GPIO1B_DS_2 0x218
29 #define GRF_GPIO1B_DS_3 0x21c
30 #define GRF_GPIO1C_DS_0 0x220
31 #define GRF_GPIO1C_DS_1 0x224
32 #define GRF_GPIO1C_DS_2 0x228
33 #define GRF_GPIO1C_DS_3 0x22c
34 #define GRF_GPIO1D_DS_0 0x230
35 #define GRF_GPIO1D_DS_1 0x234
36 #define GRF_GPIO1D_DS_2 0x238
37 #define GRF_SOC_CON4 0x510
38 #define PMU_BASE_ADDR 0xfdd90000
39 #define PMU_NOC_AUTO_CON0 (0x70)
40 #define PMU_NOC_AUTO_CON1 (0x74)
41 #define CRU_BASE 0xfdd20000
42 #define CRU_SOFTRST_CON26 0x468
43 #define CRU_SOFTRST_CON28 0x470
44 #define SGRF_BASE 0xFDD18000
45 #define SGRF_SOC_CON3 0xC
46 #define SGRF_SOC_CON4 0x10
47 #define PMUGRF_SOC_CON15 0xfdc20100
48 #define CPU_GRF_BASE 0xfdc30000
49 #define GRF_CORE_PVTPLL_CON0 (0x10)
50 #define USBPHY_U3_GRF 0xfdca0000
51 #define USBPHY_U3_GRF_CON1 (USBPHY_U3_GRF + 0x04)
52 #define USBPHY_U2_GRF 0xfdca8000
53 #define USBPHY_U2_GRF_CON0 (USBPHY_U2_GRF + 0x00)
54 #define USBPHY_U2_GRF_CON1 (USBPHY_U2_GRF + 0x04)
55
56 #define PMU_PWR_GATE_SFTCON (0xA0)
57 #define PMU_PWR_DWN_ST (0x98)
58 #define PMU_BUS_IDLE_SFTCON0 (0x50)
59 #define PMU_BUS_IDLE_ST (0x68)
60 #define PMU_BUS_IDLE_ACK (0x60)
61
62 #define EBC_PRIORITY_REG (0xfe158008)
63
64 enum {
65 /* PMU_GRF_GPIO0C_IOMUX_L */
66 GPIO0C1_SHIFT = 4,
67 GPIO0C1_MASK = GENMASK(6, 4),
68 GPIO0C1_GPIO = 0,
69 GPIO0C1_PWM2_M0,
70 GPIO0C1_NPU_AVS,
71 GPIO0C1_UART0_TX,
72 GPIO0C1_MCU_JTAGTDI,
73
74 GPIO0C0_SHIFT = 0,
75 GPIO0C0_MASK = GENMASK(2, 0),
76 GPIO0C0_GPIO = 0,
77 GPIO0C0_PWM1_M0,
78 GPIO0C0_GPU_AVS,
79 GPIO0C0_UART0_RX,
80
81 /* PMU_GRF_GPIO0D_IOMUX_L */
82 GPIO0D1_SHIFT = 4,
83 GPIO0D1_MASK = GENMASK(6, 4),
84 GPIO0D1_GPIO = 0,
85 GPIO0D1_UART2_TXM0,
86
87 GPIO0D0_SHIFT = 0,
88 GPIO0D0_MASK = GENMASK(2, 0),
89 GPIO0D0_GPIO = 0,
90 GPIO0D0_UART2_RXM0,
91
92 /* PMU_GRF_SOC_CON0 */
93 UART0_IO_SEL_SHIFT = 8,
94 UART0_IO_SEL_MASK = GENMASK(9, 8),
95 UART0_IO_SEL_M0 = 0,
96 UART0_IO_SEL_M1,
97 UART0_IO_SEL_M2,
98 };
99
100 enum {
101 /* GRF_GPIO1A_IOMUX_L */
102 GPIO1A1_SHIFT = 4,
103 GPIO1A1_MASK = GENMASK(6, 4),
104 GPIO1A1_GPIO = 0,
105 GPIO1A1_I2C3_SCLM0,
106 GPIO1A1_UART3_TXM0,
107 GPIO1A1_CAN1_TXM0,
108 GPIO1A1_AUDIOPWM_ROUT,
109 GPIO1A1_ACODEC_ADCCLK,
110 GPIO1A1_AUDIOPWM_LOUT,
111
112 GPIO1A0_SHIFT = 0,
113 GPIO1A0_MASK = GENMASK(2, 0),
114 GPIO1A0_GPIO = 0,
115 GPIO1A0_I2C3_SDAM0,
116 GPIO1A0_UART3_RXM0,
117 GPIO1A0_CAN1_RXM0,
118 GPIO1A0_AUDIOPWM_LOUT,
119 GPIO1A0_ACODEC_ADCDATA,
120 GPIO1A0_AUDIOPWM_LOUTP,
121
122 /* GRF_GPIO1A_IOMUX_H */
123 GPIO1A6_SHIFT = 8,
124 GPIO1A6_MASK = GENMASK(10, 8),
125 GPIO1A6_GPIO = 0,
126 GPIO1A6_I2S1_LRCKRXM0,
127 GPIO1A6_UART4_TXM0,
128 GPIO1A6_PDM_CLK0M0,
129 GPIO1A6_AUDIOPWM_ROUTP,
130
131 GPIO1A4_SHIFT = 0,
132 GPIO1A4_MASK = GENMASK(2, 0),
133 GPIO1A4_GPIO = 0,
134 GPIO1A4_I2S1_SCLKRXM0,
135 GPIO1A4_UART4_RXM0,
136 GPIO1A4_PDM_CLK1M0,
137 GPIO1A4_SPDIF_TXM0,
138
139 /* GRF_GPIO1D_IOMUX_H */
140 GPIO1D6_SHIFT = 8,
141 GPIO1D6_MASK = GENMASK(10, 8),
142 GPIO1D6_GPIO = 0,
143 GPIO1D6_SDMMC0_D1,
144 GPIO1D6_UART2_RXM1,
145 GPIO1D6_UART6_RXM1,
146 GPIO1D6_PWM9_M1,
147
148 GPIO1D5_SHIFT = 4,
149 GPIO1D5_MASK = GENMASK(6, 4),
150 GPIO1D5_GPIO = 0,
151 GPIO1D5_SDMMC0_D0,
152 GPIO1D5_UART2_TXM1,
153 GPIO1D5_UART6_TXM1,
154 GPIO1D5_PWM8_M1,
155
156 /* GRF_GPIO2A_IOMUX_L */
157 GPIO2A3_SHIFT = 12,
158 GPIO2A3_MASK = GENMASK(14, 12),
159 GPIO2A3_GPIO = 0,
160 GPIO2A3_SDMMC1_D0,
161 GPIO2A3_GMAC0_RXD2,
162 GPIO2A3_UART6_RXM0,
163
164 GPIO2A2_SHIFT = 8,
165 GPIO2A2_MASK = GENMASK(10, 8),
166 GPIO2A2_GPIO = 0,
167 GPIO2A2_SDMMC0_CLK,
168 GPIO2A2_TEST_CLKOUT,
169 GPIO2A2_UART5_TXM0,
170 GPIO2A2_CAN0_RXM1,
171
172 GPIO2A1_SHIFT = 4,
173 GPIO2A1_MASK = GENMASK(6, 4),
174 GPIO2A1_GPIO = 0,
175 GPIO2A1_SDMMC0_CMD,
176 GPIO2A1_PWM10_M1,
177 GPIO2A1_UART5_RXM0,
178 GPIO2A1_CAN0_TXM1,
179
180 /* GRF_GPIO2A_IOMUX_H */
181 GPIO2A7_SHIFT = 12,
182 GPIO2A7_MASK = GENMASK(14, 12),
183 GPIO2A7_GPIO = 0,
184 GPIO2A7_SDMMC1_CMD,
185 GPIO2A7_GMAC0_TXD3,
186 GPIO2A7_UART9_RXM0,
187
188 GPIO2A6_SHIFT = 8,
189 GPIO2A6_MASK = GENMASK(10, 8),
190 GPIO2A6_GPIO = 0,
191 GPIO2A6_SDMMC1_D3,
192 GPIO2A6_GMAC0_TXD2,
193 GPIO2A6_UART7_TXM0,
194
195 GPIO2A5_SHIFT = 4,
196 GPIO2A5_MASK = GENMASK(6, 4),
197 GPIO2A5_GPIO = 0,
198 GPIO2A5_SDMMC1_D2,
199 GPIO2A5_GMAC0_RXCLK,
200 GPIO2A5_UART7_RXM0,
201
202 GPIO2A4_SHIFT = 0,
203 GPIO2A4_MASK = GENMASK(2, 0),
204 GPIO2A4_GPIO = 0,
205 GPIO2A4_SDMMC1_D1,
206 GPIO2A4_GMAC0_RXD3,
207 GPIO2A4_UART6_TXM0,
208
209 /* GRF_GPIO2B_IOMUX_L */
210 GPIO2B3_SHIFT = 12,
211 GPIO2B3_MASK = GENMASK(14, 12),
212 GPIO2B3_GPIO = 0,
213 GPIO2B3_GMAC0_TXD0,
214 GPIO2B3_UART1_RXM0,
215
216 GPIO2B0_SHIFT = 0,
217 GPIO2B0_MASK = GENMASK(2, 0),
218 GPIO2B0_GPIO = 0,
219 GPIO2B0_SDMMC1_CLK,
220 GPIO2B0_GMAC0_TXCLK,
221 GPIO2B0_UART9_TXM0,
222
223 /* GRF_GPIO2B_IOMUX_H */
224 GPIO2B4_SHIFT = 0,
225 GPIO2B4_MASK = GENMASK(2, 0),
226 GPIO2B4_GPIO = 0,
227 GPIO2B4_GMAC0_TXD1,
228 GPIO2B4_UART1_TXM0,
229
230 /* GRF_GPIO2C_IOMUX_L */
231 GPIO2C2_SHIFT = 8,
232 GPIO2C2_MASK = GENMASK(10, 8),
233 GPIO2C2_GPIO = 0,
234 GPIO2C2_GMAC0_MCLKINOUT = 2,
235
236 /* GRF_GPIO2C_IOMUX_H */
237 GPIO2C6_SHIFT = 8,
238 GPIO2C6_MASK = GENMASK(10, 8),
239 GPIO2C6_GPIO = 0,
240 GPIO2C6_CLK32K_OUT1,
241 GPIO2C6_UART8_RXM0,
242 GPIO2C6_SPI1_CS1M0,
243
244 GPIO2C5_SHIFT = 4,
245 GPIO2C5_MASK = GENMASK(6, 4),
246 GPIO2C5_GPIO = 0,
247 GPIO2C5_I2S2_SDIM0,
248 GPIO2C5_GMAC0_RXER,
249 GPIO2C5_UART8_TXM0,
250 GPIO2C5_SPI2_CS1M0,
251
252 /* GRF_GPIO2D_IOMUX_H */
253 GPIO2D7_SHIFT = 12,
254 GPIO2D7_MASK = GENMASK(14, 12),
255 GPIO2D7_GPIO = 0,
256 GPIO2D7_LCDC_D7,
257 GPIO2D7_BT656_D7M0,
258 GPIO2D7_SPI2_MISOM1,
259 GPIO2D7_UART8_TXM1,
260 GPIO2D7_I2S1_SDO0M2,
261
262 /* GRF_GPIO3A_IOMUX_L */
263 GPIO3A0_SHIFT = 0,
264 GPIO3A0_MASK = GENMASK(2, 0),
265 GPIO3A0_GPIO = 0,
266 GPIO3A0_LCDC_CLK,
267 GPIO3A0_BT656_CLKM0,
268 GPIO3A0_SPI2_CLKM1,
269 GPIO3A0_UART8_RXM1,
270 GPIO3A0_I2S1_SDO1M2,
271
272 /* GRF_GPIO3B_IOMUX_L */
273 GPIO3B2_SHIFT = 8,
274 GPIO3B2_MASK = GENMASK(10, 8),
275 GPIO3B2_GPIO = 0,
276 GPIO3B2_LCDC_D17,
277 GPIO3B2_BT1120_D8,
278 GPIO3B2_GMAC1_RXD1M0,
279 GPIO3B2_UART4_TXM1,
280 GPIO3B2_PWM9_M0,
281
282 GPIO3B1_SHIFT = 4,
283 GPIO3B1_MASK = GENMASK(6, 4),
284 GPIO3B1_GPIO = 0,
285 GPIO3B1_LCDC_D16,
286 GPIO3B1_BT1120_D7,
287 GPIO3B1_GMAC1_RXD0M0,
288 GPIO3B1_UART4_RXM1,
289 GPIO3B1_PWM8_M0,
290
291 /* GRF_GPIO3B_IOMUX_H */
292 GPIO3B7_SHIFT = 12,
293 GPIO3B7_MASK = GENMASK(14, 12),
294 GPIO3B7_GPIO = 0,
295 GPIO3B7_LCDC_D22,
296 GPIO3B7_PWM12_M0,
297 GPIO3B7_GMAC1_TXENM0,
298 GPIO3B7_UART3_TXM1,
299 GPIO3B7_PDM_SDI2M2,
300
301 /* GRF_GPIO3C_IOMUX_L */
302 GPIO3C3_SHIFT = 12,
303 GPIO3C3_MASK = GENMASK(14, 12),
304 GPIO3C3_GPIO = 0,
305 GPIO3C3_LCDC_DEN,
306 GPIO3C3_BT1120_D15,
307 GPIO3C3_SPI1_CLKM1,
308 GPIO3C3_UART5_RXM1,
309 GPIO3C3_I2S1_SCLKRXM,
310
311 GPIO3C2_SHIFT = 8,
312 GPIO3C2_MASK = GENMASK(10, 8),
313 GPIO3C2_GPIO = 0,
314 GPIO3C2_LCDC_VSYNC,
315 GPIO3C2_BT1120_D14,
316 GPIO3C2_SPI1_MISOM1,
317 GPIO3C2_UART5_TXM1,
318 GPIO3C2_I2S1_SDO3M2,
319
320 GPIO3C0_SHIFT = 0,
321 GPIO3C0_MASK = GENMASK(2, 0),
322 GPIO3C0_GPIO = 0,
323 GPIO3C0_LCDC_D23,
324 GPIO3C0_PWM13_M0,
325 GPIO3C0_GMAC1_MCLKINOUTM0,
326 GPIO3C0_UART3_RXM1,
327 GPIO3C0_PDM_SDI3M2,
328
329 /* GRF_GPIO3C_IOMUX_H */
330 GPIO3C5_SHIFT = 4,
331 GPIO3C5_MASK = GENMASK(6, 4),
332 GPIO3C5_GPIO = 0,
333 GPIO3C5_PWM15_IRM0,
334 GPIO3C5_SPDIF_TXM1,
335 GPIO3C5_GMAC1_MDIOM0,
336 GPIO3C5_UART7_RXM1,
337 GPIO3C5_I2S1_LRCKRXM2,
338
339 GPIO3C4_SHIFT = 0,
340 GPIO3C4_MASK = GENMASK(2, 0),
341 GPIO3C4_GPIO = 0,
342 GPIO3C4_PWM14_M0,
343 GPIO3C4_VOP_PWMM1,
344 GPIO3C4_GMAC1_MDCM0,
345 GPIO3C4_UART7_TXM1,
346 GPIO3C4_PDM_CLK1M2,
347
348 /* GRF_GPIO3D_IOMUX_H */
349 GPIO3D7_SHIFT = 12,
350 GPIO3D7_MASK = GENMASK(14, 12),
351 GPIO3D7_GPIO = 0,
352 GPIO3D7_CIF_D9,
353 GPIO3D7_EBC_SDDO9,
354 GPIO3D7_GMAC1_TXD3M1,
355 GPIO3D7_UART1_RXM1,
356 GPIO3D7_PDM_SDI0M1,
357
358 GPIO3D6_SHIFT = 8,
359 GPIO3D6_MASK = GENMASK(10, 8),
360 GPIO3D6_GPIO = 0,
361 GPIO3D6_CIF_D8,
362 GPIO3D6_EBC_SDDO8,
363 GPIO3D6_GMAC1_TXD2M1,
364 GPIO3D6_UART1_TXM1,
365 GPIO3D6_PDM_CLK0M1,
366
367 /* GRF_GPIO4A_IOMUX_L */
368 GPIO4A3_SHIFT = 12,
369 GPIO4A3_MASK = GENMASK(14, 12),
370 GPIO4A3_GPIO = 0,
371 GPIO4A3_CIF_D13,
372 GPIO4A3_EBC_SDDO13,
373 GPIO4A3_GMAC1_RXCLKM1,
374 GPIO4A3_UART7_RXM2,
375 GPIO4A3_PDM_SDI3M1,
376
377 GPIO4A2_SHIFT = 8,
378 GPIO4A2_MASK = GENMASK(10, 8),
379 GPIO4A2_GPIO = 0,
380 GPIO4A2_CIF_D12,
381 GPIO4A2_EBC_SDDO12,
382 GPIO4A2_GMAC1_RXD3M1,
383 GPIO4A2_UART7_TXM2,
384 GPIO4A2_PDM_SDI2M1,
385
386 /* GRF_GPIO4A_IOMUX_H */
387 GPIO4A5_SHIFT = 4,
388 GPIO4A5_MASK = GENMASK(6, 4),
389 GPIO4A5_GPIO = 0,
390 GPIO4A5_CIF_D15,
391 GPIO4A5_EBC_SDDO15,
392 GPIO4A5_GMAC1_TXD1M1,
393 GPIO4A5_UART9_RXM2,
394 GPIO4A5_I2S2_LRCKRXM1,
395
396 GPIO4A4_SHIFT = 0,
397 GPIO4A4_MASK = GENMASK(2, 0),
398 GPIO4A4_GPIO = 0,
399 GPIO4A4_CIF_D14,
400 GPIO4A4_EBC_SDDO14,
401 GPIO4A4_GMAC1_TXD0M1,
402 GPIO4A4_UART9_TXM2,
403 GPIO4A4_I2S2_LRCKTXM1,
404
405 /* GRF_GPIO4C_IOMUX_L */
406 GPIO4C1_SHIFT = 4,
407 GPIO4C1_MASK = GENMASK(6, 4),
408 GPIO4C1_GPIO = 0,
409 GPIO4C1_CIF_CLKIN,
410 GPIO4C1_EBC_SDCLK,
411 GPIO4C1_GMAC1_MCLKINOUTM1,
412
413 /* GRF_GPIO4C_IOMUX_H */
414 GPIO4C6_SHIFT = 8,
415 GPIO4C6_MASK = GENMASK(10, 8),
416 GPIO4C6_GPIO = 0,
417 GPIO4C6_PWM13_M1,
418 GPIO4C6_SPI3_CS0M1,
419 GPIO4C6_SATA0_ACTLED,
420 GPIO4C6_UART9_RXM1,
421 GPIO4C6_I2S3_SDIM1,
422
423 GPIO4C5_SHIFT = 4,
424 GPIO4C5_MASK = GENMASK(6, 4),
425 GPIO4C5_GPIO = 0,
426 GPIO4C5_PWM12_M1,
427 GPIO4C5_SPI3_MISOM1,
428 GPIO4C5_SATA1_ACTLED,
429 GPIO4C5_UART9_TXM1,
430 GPIO4C5_I2S3_SDOM1,
431
432 /* GRF_IOFUNC_SEL3 */
433 UART4_IO_SEL_SHIFT = 14,
434 UART4_IO_SEL_MASK = GENMASK(14, 14),
435 UART4_IO_SEL_M0 = 0,
436 UART4_IO_SEL_M1,
437
438 UART3_IO_SEL_SHIFT = 12,
439 UART3_IO_SEL_MASK = GENMASK(12, 12),
440 UART3_IO_SEL_M0 = 0,
441 UART3_IO_SEL_M1,
442
443 UART2_IO_SEL_SHIFT = 10,
444 UART2_IO_SEL_MASK = GENMASK(11, 10),
445 UART2_IO_SEL_M0 = 0,
446 UART2_IO_SEL_M1,
447
448 UART1_IO_SEL_SHIFT = 8,
449 UART1_IO_SEL_MASK = GENMASK(8, 8),
450 UART1_IO_SEL_M0 = 0,
451 UART1_IO_SEL_M1,
452
453 /* GRF_IOFUNC_SEL4 */
454 UART9_IO_SEL_SHIFT = 8,
455 UART9_IO_SEL_MASK = GENMASK(9, 8),
456 UART9_IO_SEL_M0 = 0,
457 UART9_IO_SEL_M1,
458 UART9_IO_SEL_M2,
459
460 UART8_IO_SEL_SHIFT = 6,
461 UART8_IO_SEL_MASK = GENMASK(6, 6),
462 UART8_IO_SEL_M0 = 0,
463 UART8_IO_SEL_M1,
464
465 UART7_IO_SEL_SHIFT = 4,
466 UART7_IO_SEL_MASK = GENMASK(5, 4),
467 UART7_IO_SEL_M0 = 0,
468 UART7_IO_SEL_M1,
469 UART7_IO_SEL_M2,
470
471 UART6_IO_SEL_SHIFT = 2,
472 UART6_IO_SEL_MASK = GENMASK(2, 2),
473 UART6_IO_SEL_M0 = 0,
474 UART6_IO_SEL_M1,
475
476 UART5_IO_SEL_SHIFT = 0,
477 UART5_IO_SEL_MASK = GENMASK(0, 0),
478 UART5_IO_SEL_M0 = 0,
479 UART5_IO_SEL_M1,
480 };
481
482 #ifdef CONFIG_ARM64
483 #include <asm/armv8/mmu.h>
484
485 static struct mm_region rk3568_mem_map[] = {
486 {
487 .virt = 0x0UL,
488 .phys = 0x0UL,
489 .size = 0xf0000000UL,
490 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
491 PTE_BLOCK_INNER_SHARE
492 }, {
493 .virt = 0xf0000000UL,
494 .phys = 0xf0000000UL,
495 .size = 0x10000000UL,
496 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
497 PTE_BLOCK_NON_SHARE |
498 PTE_BLOCK_PXN | PTE_BLOCK_UXN
499 }, {
500 .virt = 0x300000000,
501 .phys = 0x300000000,
502 .size = 0x0c0c00000,
503 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
504 PTE_BLOCK_NON_SHARE |
505 PTE_BLOCK_PXN | PTE_BLOCK_UXN
506 }, {
507 /* List terminator */
508 0,
509 }
510 };
511
512 struct mm_region *mem_map = rk3568_mem_map;
513 #endif
514
board_debug_uart_init(void)515 void board_debug_uart_init(void)
516 {
517 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfdd50000)
518 static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
519 /* UART0 M0 */
520 rk_clrsetreg(&pmugrf->pmu_soc_con0, UART0_IO_SEL_MASK,
521 UART0_IO_SEL_M0 << UART0_IO_SEL_SHIFT);
522
523 /* Switch iomux */
524 rk_clrsetreg(&pmugrf->pmu_gpio0c_iomux_l,
525 GPIO0C1_MASK | GPIO0C0_MASK,
526 GPIO0C1_UART0_TX << GPIO0C1_SHIFT |
527 GPIO0C0_UART0_RX << GPIO0C0_SHIFT);
528
529 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe650000)
530 static struct rk3568_grf * const grf = (void *)GRF_BASE;
531
532 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
533 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
534 /* UART1 M0 */
535 rk_clrsetreg(&grf->iofunc_sel3, UART1_IO_SEL_MASK,
536 UART1_IO_SEL_M0 << UART1_IO_SEL_SHIFT);
537
538 /* Switch iomux */
539 rk_clrsetreg(&grf->gpio2b_iomux_l,
540 GPIO2B3_MASK, GPIO2B3_UART1_RXM0 << GPIO2B3_SHIFT);
541 rk_clrsetreg(&grf->gpio2b_iomux_h,
542 GPIO2B4_MASK, GPIO2B4_UART1_TXM0 << GPIO2B4_SHIFT);
543 #else
544 /* UART1 M1 */
545 rk_clrsetreg(&grf->iofunc_sel3, UART1_IO_SEL_MASK,
546 UART1_IO_SEL_M1 << UART1_IO_SEL_SHIFT);
547
548 /* Switch iomux */
549 rk_clrsetreg(&grf->gpio3d_iomux_h,
550 GPIO3D7_MASK | GPIO3D6_MASK,
551 GPIO3D7_UART1_RXM1 << GPIO3D7_SHIFT |
552 GPIO3D6_UART1_TXM1 << GPIO3D6_SHIFT);
553 #endif
554 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe660000)
555 static struct rk3568_grf * const grf = (void *)GRF_BASE;
556
557 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
558 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
559 static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
560 /* UART2 M0 */
561 rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
562 UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
563
564 /* Switch iomux */
565 rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
566 GPIO0D1_MASK | GPIO0D0_MASK,
567 GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
568 GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
569 #else
570 /* UART2 M1 */
571 rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
572 UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
573
574 /* Switch iomux */
575 rk_clrsetreg(&grf->gpio1d_iomux_h,
576 GPIO1D6_MASK | GPIO1D5_MASK,
577 GPIO1D6_UART2_RXM1 << GPIO1D6_SHIFT |
578 GPIO1D5_UART2_TXM1 << GPIO1D5_SHIFT);
579 #endif
580 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe670000)
581 static struct rk3568_grf * const grf = (void *)GRF_BASE;
582
583 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
584 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
585 /* UART3 M0 */
586 rk_clrsetreg(&grf->iofunc_sel3, UART3_IO_SEL_MASK,
587 UART3_IO_SEL_M0 << UART3_IO_SEL_SHIFT);
588
589 /* Switch iomux */
590 rk_clrsetreg(&grf->gpio1a_iomux_l,
591 GPIO1A1_MASK | GPIO1A0_MASK,
592 GPIO1A1_UART3_TXM0 << GPIO1A1_SHIFT |
593 GPIO1A0_UART3_RXM0 << GPIO1A0_SHIFT);
594 #else
595 /* UART3 M1 */
596 rk_clrsetreg(&grf->iofunc_sel3, UART3_IO_SEL_MASK,
597 UART3_IO_SEL_M1 << UART3_IO_SEL_SHIFT);
598
599 /* Switch iomux */
600 rk_clrsetreg(&grf->gpio3b_iomux_h,
601 GPIO3B7_MASK, GPIO3B7_UART3_TXM1 << GPIO3B7_SHIFT);
602 rk_clrsetreg(&grf->gpio3c_iomux_l,
603 GPIO3C0_MASK, GPIO3C0_UART3_RXM1 << GPIO3C0_SHIFT);
604 #endif
605 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe680000)
606 static struct rk3568_grf * const grf = (void *)GRF_BASE;
607
608 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
609 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
610 /* UART4 M0 */
611 rk_clrsetreg(&grf->iofunc_sel3, UART4_IO_SEL_MASK,
612 UART4_IO_SEL_M0 << UART4_IO_SEL_SHIFT);
613
614 /* Switch iomux */
615 rk_clrsetreg(&grf->gpio1a_iomux_h,
616 GPIO1A6_MASK | GPIO1A4_MASK,
617 GPIO1A6_UART4_TXM0 << GPIO1A6_SHIFT |
618 GPIO1A4_UART4_RXM0 << GPIO1A4_SHIFT);
619 #else
620 /* UART4 M1 */
621 rk_clrsetreg(&grf->iofunc_sel3, UART4_IO_SEL_MASK,
622 UART4_IO_SEL_M1 << UART4_IO_SEL_SHIFT);
623
624 /* Switch iomux */
625 rk_clrsetreg(&grf->gpio3b_iomux_l,
626 GPIO3B2_MASK | GPIO3B1_MASK,
627 GPIO3B2_UART4_TXM1 << GPIO3B2_SHIFT |
628 GPIO3B1_UART4_RXM1 << GPIO3B1_SHIFT);
629 #endif
630 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe690000)
631 static struct rk3568_grf * const grf = (void *)GRF_BASE;
632
633 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
634 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
635 /* UART5 M0 */
636 rk_clrsetreg(&grf->iofunc_sel4, UART5_IO_SEL_MASK,
637 UART5_IO_SEL_M0 << UART5_IO_SEL_SHIFT);
638
639 /* Switch iomux */
640 rk_clrsetreg(&grf->gpio2a_iomux_l,
641 GPIO2A2_MASK | GPIO2A1_MASK,
642 GPIO2A2_UART5_TXM0 << GPIO2A2_SHIFT |
643 GPIO2A1_UART5_RXM0 << GPIO2A1_SHIFT);
644 #else
645 /* UART5 M1 */
646 rk_clrsetreg(&grf->iofunc_sel4, UART5_IO_SEL_MASK,
647 UART5_IO_SEL_M1 << UART5_IO_SEL_SHIFT);
648
649 /* Switch iomux */
650 rk_clrsetreg(&grf->gpio3c_iomux_l,
651 GPIO3C3_MASK | GPIO3C2_MASK,
652 GPIO3C3_UART5_RXM1 << GPIO3C3_SHIFT |
653 GPIO3C2_UART5_TXM1 << GPIO3C2_SHIFT);
654 #endif
655 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6a0000)
656 static struct rk3568_grf * const grf = (void *)GRF_BASE;
657
658 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
659 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
660 /* UART6 M0 */
661 rk_clrsetreg(&grf->iofunc_sel4, UART6_IO_SEL_MASK,
662 UART6_IO_SEL_M0 << UART6_IO_SEL_SHIFT);
663
664 /* Switch iomux */
665 rk_clrsetreg(&grf->gpio2a_iomux_l,
666 GPIO2A3_MASK, GPIO2A3_UART6_RXM0 << GPIO2A3_SHIFT);
667 rk_clrsetreg(&grf->gpio2a_iomux_h,
668 GPIO2A4_MASK, GPIO2A4_UART6_TXM0 << GPIO2A4_SHIFT);
669 #else
670 /* UART6 M1 */
671 rk_clrsetreg(&grf->iofunc_sel4, UART6_IO_SEL_MASK,
672 UART6_IO_SEL_M1 << UART6_IO_SEL_SHIFT);
673
674 /* Switch iomux */
675 rk_clrsetreg(&grf->gpio1d_iomux_h,
676 GPIO1D6_MASK | GPIO1D5_MASK,
677 GPIO1D6_UART6_RXM1 << GPIO1D6_SHIFT |
678 GPIO1D5_UART6_TXM1 << GPIO1D5_SHIFT);
679 #endif
680 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6b0000)
681 static struct rk3568_grf * const grf = (void *)GRF_BASE;
682
683 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
684 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
685 /* UART7 M0 */
686 rk_clrsetreg(&grf->iofunc_sel4, UART7_IO_SEL_MASK,
687 UART7_IO_SEL_M0 << UART7_IO_SEL_SHIFT);
688
689 /* Switch iomux */
690 rk_clrsetreg(&grf->gpio2a_iomux_h,
691 GPIO2A6_MASK | GPIO2A5_MASK,
692 GPIO2A6_UART7_TXM0 << GPIO2A6_SHIFT |
693 GPIO2A5_UART7_RXM0 << GPIO2A5_SHIFT);
694 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
695 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
696 /* UART7 M1 */
697 rk_clrsetreg(&grf->iofunc_sel4, UART7_IO_SEL_MASK,
698 UART7_IO_SEL_M1 << UART7_IO_SEL_SHIFT);
699
700 /* Switch iomux */
701 rk_clrsetreg(&grf->gpio3c_iomux_h,
702 GPIO3C5_MASK | GPIO3C4_MASK,
703 GPIO3C5_UART7_RXM1 << GPIO3C5_SHIFT |
704 GPIO3C4_UART7_TXM1 << GPIO3C4_SHIFT);
705 #else
706 /* UART7 M2 */
707 rk_clrsetreg(&grf->iofunc_sel4, UART7_IO_SEL_MASK,
708 UART7_IO_SEL_M2 << UART7_IO_SEL_SHIFT);
709
710 /* Switch iomux */
711 rk_clrsetreg(&grf->gpio4a_iomux_l,
712 GPIO4A3_MASK | GPIO4A2_MASK,
713 GPIO4A3_UART7_RXM2 << GPIO4A3_SHIFT |
714 GPIO4A2_UART7_TXM2 << GPIO4A2_SHIFT);
715 #endif
716 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6c0000)
717 static struct rk3568_grf * const grf = (void *)GRF_BASE;
718
719 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
720 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
721 /* UART8 M0 */
722 rk_clrsetreg(&grf->iofunc_sel4, UART8_IO_SEL_MASK,
723 UART8_IO_SEL_M0 << UART8_IO_SEL_SHIFT);
724
725 /* Switch iomux */
726 rk_clrsetreg(&grf->gpio2c_iomux_h,
727 GPIO2C6_MASK | GPIO2C5_MASK,
728 GPIO2C6_UART8_RXM0 << GPIO2C6_SHIFT |
729 GPIO2C5_UART8_TXM0 << GPIO2C5_SHIFT);
730 #else
731 /* UART8 M1 */
732 rk_clrsetreg(&grf->iofunc_sel4, UART8_IO_SEL_MASK,
733 UART8_IO_SEL_M1 << UART8_IO_SEL_SHIFT);
734
735 /* Switch iomux */
736 rk_clrsetreg(&grf->gpio2d_iomux_h,
737 GPIO2D7_MASK | GPIO3A0_MASK,
738 GPIO2D7_UART8_TXM1 << GPIO2D7_SHIFT |
739 GPIO3A0_UART8_RXM1 << GPIO3A0_SHIFT);
740 #endif
741 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6d0000)
742 static struct rk3568_grf * const grf = (void *)GRF_BASE;
743
744 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
745 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
746 /* UART9 M0 */
747 rk_clrsetreg(&grf->iofunc_sel4, UART9_IO_SEL_MASK,
748 UART9_IO_SEL_M0 << UART9_IO_SEL_SHIFT);
749
750 /* Switch iomux */
751 rk_clrsetreg(&grf->gpio2a_iomux_h,
752 GPIO2A7_MASK, GPIO2A7_UART9_RXM0 << GPIO2A7_SHIFT);
753 rk_clrsetreg(&grf->gpio2b_iomux_l,
754 GPIO2B0_MASK, GPIO2B0_UART9_TXM0 << GPIO2B0_SHIFT);
755 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
756 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
757 /* UART9 M1 */
758 rk_clrsetreg(&grf->iofunc_sel4, UART9_IO_SEL_MASK,
759 UART9_IO_SEL_M1 << UART9_IO_SEL_SHIFT);
760
761 /* Switch iomux */
762 rk_clrsetreg(&grf->gpio4c_iomux_h,
763 GPIO4C6_MASK | GPIO4C5_MASK,
764 GPIO4C6_UART9_RXM1 << GPIO4C6_SHIFT |
765 GPIO4C5_UART9_TXM1 << GPIO4C5_SHIFT);
766 #else
767 /* UART9 M2 */
768 rk_clrsetreg(&grf->iofunc_sel4, UART9_IO_SEL_MASK,
769 UART9_IO_SEL_M2 << UART9_IO_SEL_SHIFT);
770
771 /* Switch iomux */
772 rk_clrsetreg(&grf->gpio4a_iomux_h,
773 GPIO4A5_MASK | GPIO4A4_MASK,
774 GPIO4A5_UART9_RXM2 << GPIO4A5_SHIFT |
775 GPIO4A4_UART9_TXM2 << GPIO4A4_SHIFT);
776 #endif
777 #endif
778 }
779
fit_standalone_release(char * id,uintptr_t entry_point)780 int fit_standalone_release(char *id, uintptr_t entry_point)
781 {
782 /* risc-v configuration: */
783 /* Reset the scr1 */
784 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26);
785 udelay(100);
786
787 /* set the scr1 addr */
788 writel((0xffff0000) | (entry_point >> 16), GRF_BASE + GRF_SOC_CON4);
789 udelay(10);
790
791 /* release the scr1 */
792 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26);
793
794 return 0;
795 }
796
797 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
qos_priority_init(void)798 static void qos_priority_init(void)
799 {
800 u32 delay;
801
802 /* enable all pd except npu and gpu */
803 writel(0xffff0000 & ~(BIT(0 + 16) | BIT(1 + 16)),
804 PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
805 delay = 1000;
806 do {
807 udelay(1);
808 delay--;
809 if (delay == 0) {
810 printf("Fail to set domain.");
811 hang();
812 }
813 } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & ~(BIT(0) | BIT(1)));
814
815 /* release all idle request except npu and gpu */
816 writel(0xffff0000 & ~(BIT(1 + 16) | BIT(2 + 16)),
817 PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON0);
818
819 delay = 1000;
820 /* wait ack status */
821 do {
822 udelay(1);
823 delay--;
824 if (delay == 0) {
825 printf("Fail to get ack on domain.\n");
826 hang();
827 }
828 } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK) & ~(BIT(1) | BIT(2)));
829
830 delay = 1000;
831 /* wait idle status */
832 do {
833 udelay(1);
834 delay--;
835 if (delay == 0) {
836 printf("Fail to set idle on domain.\n");
837 hang();
838 }
839 } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST) & ~(BIT(1) | BIT(2)));
840
841 writel(0x303, EBC_PRIORITY_REG);
842 }
843 #endif
844
arch_cpu_init(void)845 int arch_cpu_init(void)
846 {
847 #ifdef CONFIG_SPL_BUILD
848 /*
849 * When perform idle operation, corresponding clock can
850 * be opened or gated automatically.
851 */
852 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
853 writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
854
855 /* Set the emmc sdmmc0 to secure */
856 writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
857 /* set the emmc ds to level 2 */
858 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
859 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
860 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
861 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
862 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
863 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
864
865 #if defined(CONFIG_ROCKCHIP_SFC)
866 /* Set the fspi to secure */
867 writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
868 #endif
869
870 #ifndef CONFIG_TPL_BUILD
871 /* set the fspi d0~3 cs0 to level 2 */
872 if (get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NOR ||
873 get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NAND) {
874 writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3);
875 writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0);
876 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1);
877 writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2);
878 }
879 #endif
880
881 /* Set core pvtpll ring length */
882 writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
883
884 /*
885 * Assert reset the pipephy0, pipephy1 and pipephy2,
886 * and de-assert reset them in Kernel combphy driver.
887 */
888 writel(0x02a002a0, CRU_BASE + CRU_SOFTRST_CON28);
889
890 /*
891 * Set USB 2.0 PHY0 port1 and PHY1 port0 and port1
892 * enter suspend mode to to save power. And USB 2.0
893 * PHY0 port0 for OTG interface still in normal mode.
894 */
895 writel(0x01ff01d1, USBPHY_U3_GRF_CON1);
896 writel(0x01ff01d1, USBPHY_U2_GRF_CON0);
897 writel(0x01ff01d1, USBPHY_U2_GRF_CON1);
898
899 #ifndef CONFIG_TPL_BUILD
900 qos_priority_init();
901 #endif
902 static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
903 rk_clrsetreg(&pmugrf->pmu_gpio0b_iomux_l,
904 GENMASK(10, 8) | GENMASK(6, 4),
905 1 << 8 |
906 1 << 4);
907 #elif defined(CONFIG_SUPPORT_USBPLUG)
908 /*
909 * When perform idle operation, corresponding clock can
910 * be opened or gated automatically.
911 */
912 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
913 writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
914
915 writel(0x00030000, SGRF_BASE + SGRF_SOC_CON4); /* usb3otg0 master secure setting */
916
917 /* Set the emmc sdmmc0 to secure */
918 writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
919 /* set the emmc ds to level 2 */
920 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
921 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
922 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
923 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
924 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
925 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
926
927 /* emmc and sfc iomux */
928 writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
929 writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
930 writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
931 writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
932 writel(((7 << 0) << 16) | (1 << 0), GRF_BASE + GRF_GPIO1D_IOMUX_H);
933
934 /* Set the fspi to secure */
935 writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
936 #else /* U-Boot */
937 /* uboot: config iomux */
938 #if defined(CONFIG_ROCKCHIP_SFC_IOMUX)
939 writel((0x70002000), GRF_BASE + GRF_GPIO1C_IOMUX_H);
940 writel((0x77771111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
941 writel((0x00070001), GRF_BASE + GRF_GPIO1D_IOMUX_H);
942 #elif defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
943 writel((0x77771111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
944 writel((0x77771111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
945 writel((0x07770111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
946 #endif
947 #endif
948
949 return 0;
950 }
951
952 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)953 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
954 {
955 /* Reset the scr1 */
956 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26);
957 udelay(100);
958 /* set the scr1 addr */
959 writel((0xffff0000) | (entry_point >> 16), GRF_BASE + GRF_SOC_CON4);
960 udelay(10);
961 /* release the scr1 */
962 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26);
963
964 return 0;
965 }
966 #endif
967
968 #if CONFIG_IS_ENABLED(CLK_SCMI)
969 #include <dm.h>
970 /*
971 * armclk: 1104M:
972 * rockchip,clk-init = <1104000000>,
973 * vdd_cpu : regulator-init-microvolt = <825000>;
974 * armclk: 1416M(by default):
975 * rockchip,clk-init = <1416000000>,
976 * vdd_cpu : regulator-init-microvolt = <900000>;
977 * armclk: 1608M:
978 * rockchip,clk-init = <1608000000>,
979 * vdd_cpu : regulator-init-microvolt = <975000>;
980 */
981
set_armclk_rate(void)982 int set_armclk_rate(void)
983 {
984 struct clk clk;
985 u32 *rates = NULL;
986 int ret, size, num_rates;
987
988 ret = rockchip_get_scmi_clk(&clk.dev);
989 if (ret) {
990 printf("Failed to get scmi clk dev\n");
991 return ret;
992 }
993
994 size = dev_read_size(clk.dev, "rockchip,clk-init");
995 if (size < 0)
996 return 0;
997
998 num_rates = size / sizeof(u32);
999 rates = calloc(num_rates, sizeof(u32));
1000 if (!rates)
1001 return -ENOMEM;
1002
1003 ret = dev_read_u32_array(clk.dev, "rockchip,clk-init",
1004 rates, num_rates);
1005 if (ret) {
1006 printf("Cannot get rockchip,clk-init reg\n");
1007 return -EINVAL;
1008 }
1009 clk.id = 0;
1010 ret = clk_set_rate(&clk, rates[clk.id]);
1011 if (ret < 0) {
1012 printf("Failed to set armclk\n");
1013 return ret;
1014 }
1015 return 0;
1016 }
1017 #endif
1018
1019 #define CRU_NODE_FDT_PATH "/clock-controller@fdd20000"
1020 #define CRU_RATE_CNT_MIN 6
1021 #define CRU_PARENT_CNT_MIN 3
1022
1023 #define RKVDEC_NODE_FDT_PATH "/rkvdec@fdf80200"
1024 #define RKVDEC_NORMAL_RATE_CNT_MIN 5
1025 #define RKVDEC_RATE_CNT_MIN 4
1026
1027 #define GMAC0_NODE_FDT_PATH "/ethernet@fe2a0000"
1028 #define GMAC1_NODE_FDT_PATH "/ethernet@fe010000"
1029
1030 #define GMAC0_CLKIN_NODE_FDT_PATH "/external-gmac0-clock"
1031 #define GMAC1_CLKIN_NODE_FDT_PATH "/external-gmac1-clock"
1032
1033 #define GMAC1M0_MIIM_PINCTRL_PATH "/pinctrl/gmac1/gmac1m0-miim"
1034
rk3568_board_fdt_fixup_ethernet(const void * blob,int id)1035 static int rk3568_board_fdt_fixup_ethernet(const void *blob, int id)
1036 {
1037 int gmac_node, clkin_node, miim_node, len;
1038 const char *gmac_path, *clkin_path;
1039 void *fdt = (void *)gd->fdt_blob;
1040 u32 phandle, *pp;
1041
1042 /* get the gmac node and clockin node path at DTB */
1043 if (id == 1) {
1044 gmac_path = GMAC1_NODE_FDT_PATH;
1045 clkin_path = GMAC1_CLKIN_NODE_FDT_PATH;
1046 } else {
1047 gmac_path = GMAC0_NODE_FDT_PATH;
1048 clkin_path = GMAC0_CLKIN_NODE_FDT_PATH;
1049 }
1050
1051 gmac_node = fdt_path_offset(gd->fdt_blob, gmac_path);
1052 if (gmac_node < 0)
1053 return 0;
1054
1055 /* only fixes the RGMII clock input mode for gmac node */
1056 if (fdt_stringlist_search(fdt, gmac_node,
1057 "status", "disabled") < 0) {
1058 if (fdt_stringlist_search(fdt, gmac_node,
1059 "phy-mode", "rgmii") >= 0) {
1060 if (fdt_stringlist_search(fdt, gmac_node,
1061 "clock_in_out", "output") >= 0) {
1062 struct rk3568_grf *grf = (void *)GRF_BASE;
1063
1064 clkin_node = fdt_path_offset(fdt, clkin_path);
1065 if (clkin_node < 0)
1066 return 0;
1067 phandle = fdt_get_phandle(blob, clkin_node);
1068 if (!phandle)
1069 return 0;
1070 /*
1071 * before fixed:
1072 * assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
1073 * after fixed:
1074 * assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac_clkin 0>;
1075 */
1076 pp = (u32 *)fdt_getprop(blob, gmac_node,
1077 "assigned-clock-parents",
1078 &len);
1079 if (!pp)
1080 return 0;
1081 if ((len / 8) >= 2) {
1082 pp[2] = cpu_to_fdt32(phandle);
1083 pp[3] = cpu_to_fdt32(0);
1084 }
1085
1086 /*
1087 * before fixed:
1088 * clock_in_out = "output";
1089 * after fixed:
1090 * clock_in_out = "input";
1091 */
1092
1093 do_fixup_by_path(fdt, gmac_path, "clock_in_out",
1094 "input", 6, 0);
1095 /*
1096 * set gmac_clkinout pin iomux for rgmii
1097 * input mode.
1098 */
1099 if (!id) {
1100 rk_clrsetreg(&grf->gpio2c_iomux_l,
1101 GPIO2C2_MASK,
1102 GPIO2C2_GMAC0_MCLKINOUT << GPIO2C2_SHIFT);
1103 } else {
1104 /*
1105 * get the miim pins phandle to check
1106 * m0 or m1 for gmac1_clkinout.
1107 */
1108 miim_node = fdt_path_offset(fdt,
1109 GMAC1M0_MIIM_PINCTRL_PATH);
1110 if (miim_node < 0)
1111 goto gmac1_mclkinoutm1;
1112 phandle = fdt_get_phandle(blob, miim_node);
1113 if (!phandle)
1114 goto gmac1_mclkinoutm1;
1115
1116 pp = (u32 *)fdt_getprop(blob, gmac_node, "pinctrl-0", &len);
1117 if (!pp)
1118 goto gmac1_mclkinoutm1;
1119 if (pp[0] == cpu_to_fdt32(phandle)) {
1120 rk_clrsetreg(&grf->gpio3c_iomux_l,
1121 GPIO3C0_MASK,
1122 GPIO3C0_GMAC1_MCLKINOUTM0 << GPIO3C0_SHIFT);
1123 return 0;
1124 }
1125 gmac1_mclkinoutm1:
1126 rk_clrsetreg(&grf->gpio4c_iomux_l,
1127 GPIO4C1_MASK,
1128 GPIO4C1_GMAC1_MCLKINOUTM1 << GPIO4C1_SHIFT);
1129 }
1130 }
1131 }
1132 }
1133
1134 return 0;
1135 }
1136
rk_board_fdt_fixup(const void * blob)1137 int rk_board_fdt_fixup(const void *blob)
1138 {
1139 int node, len;
1140 u32 *pp;
1141
1142 /* Don't go further if new variant */
1143 if (rockchip_get_cpu_version() > 0)
1144 return 0;
1145
1146 node = fdt_path_offset(blob, CRU_NODE_FDT_PATH);
1147 if (node < 0)
1148 return 0;
1149
1150 /*
1151 * fixup as:
1152 * rate[1] = <400000000>; // ACLK_RKVDEC_PRE
1153 * rate[2] = <400000000>; // CLK_RKVDEC_CORE
1154 * rate[5] = <400000000>; // PLL_CPLL
1155 */
1156 pp = (u32 *)fdt_getprop(blob, node, "assigned-clock-rates", &len);
1157 if (!pp)
1158 return 0;
1159 if ((len / 4) >= CRU_RATE_CNT_MIN) {
1160 pp[1] = cpu_to_fdt32(400000000);
1161 pp[2] = cpu_to_fdt32(400000000);
1162 pp[5] = cpu_to_fdt32(400000000);
1163 }
1164
1165 /*
1166 * fixup as:
1167 * parents[1] = <&cru PLL_CPLL>;
1168 * parents[2] = <&cru PLL_CPLL>;
1169 */
1170 pp = (u32 *)fdt_getprop(blob, node, "assigned-clock-parents", &len);
1171 if (!pp)
1172 return 0;
1173 if ((len / 8) >= CRU_PARENT_CNT_MIN) {
1174 pp[3] = cpu_to_fdt32(PLL_CPLL);
1175 pp[5] = cpu_to_fdt32(PLL_CPLL);
1176 }
1177
1178 node = fdt_path_offset(blob, RKVDEC_NODE_FDT_PATH);
1179 if (node < 0)
1180 return 0;
1181 pp = (u32 *)fdt_getprop(blob, node, "rockchip,normal-rates", &len);
1182 if (!pp)
1183 return 0;
1184
1185 if ((len / 4) >= RKVDEC_NORMAL_RATE_CNT_MIN) {
1186 pp[0] = cpu_to_fdt32(400000000);
1187 pp[1] = cpu_to_fdt32(0);
1188 pp[2] = cpu_to_fdt32(400000000);
1189 pp[3] = cpu_to_fdt32(400000000);
1190 pp[4] = cpu_to_fdt32(400000000);
1191 }
1192
1193 pp = (u32 *)fdt_getprop(blob, node, "assigned-clock-rates", &len);
1194 if (!pp)
1195 return 0;
1196
1197 if ((len / 4) >= RKVDEC_RATE_CNT_MIN) {
1198 pp[0] = cpu_to_fdt32(400000000);
1199 pp[1] = cpu_to_fdt32(400000000);
1200 pp[2] = cpu_to_fdt32(400000000);
1201 pp[3] = cpu_to_fdt32(400000000);
1202 }
1203
1204 rk3568_board_fdt_fixup_ethernet(blob, 0);
1205 rk3568_board_fdt_fixup_ethernet(blob, 1);
1206
1207 return 0;
1208 }
1209
1210 // #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ROCKCHIP_DMC_FSP)
1211 #if 0
1212 int rk_board_init(void)
1213 {
1214 struct udevice *dev;
1215 u32 ret = 0;
1216
1217 ret = uclass_get_device_by_driver(UCLASS_DMC, DM_GET_DRIVER(dmc_fsp), &dev);
1218 if (ret) {
1219 printf("dmc_fsp failed, ret=%d\n", ret);
1220 return 0;
1221 }
1222
1223 return 0;
1224 }
1225 #endif
1226