1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <dm.h> 9*4882a593Smuzhiyun #include <syscon.h> 10*4882a593Smuzhiyun #include <asm/arch/clock.h> 11*4882a593Smuzhiyun #include <asm/arch/cru_rk3562.h> 12*4882a593Smuzhiyun rockchip_get_clk(struct udevice ** devp)13*4882a593Smuzhiyunint rockchip_get_clk(struct udevice **devp) 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun return uclass_get_device_by_driver(UCLASS_CLK, 16*4882a593Smuzhiyun DM_GET_DRIVER(rockchip_rk3562_cru), devp); 17*4882a593Smuzhiyun } 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(CLK_SCMI) rockchip_get_scmi_clk(struct udevice ** devp)20*4882a593Smuzhiyunint rockchip_get_scmi_clk(struct udevice **devp) 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun return uclass_get_device_by_driver(UCLASS_CLK, 23*4882a593Smuzhiyun DM_GET_DRIVER(scmi_clock), devp); 24*4882a593Smuzhiyun } 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun rockchip_get_cru(void)27*4882a593Smuzhiyunvoid *rockchip_get_cru(void) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun struct rk3562_clk_priv *priv; 30*4882a593Smuzhiyun struct udevice *dev; 31*4882a593Smuzhiyun int ret; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun ret = rockchip_get_clk(&dev); 34*4882a593Smuzhiyun if (ret) 35*4882a593Smuzhiyun return ERR_PTR(ret); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun priv = dev_get_priv(dev); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun return priv->cru; 40*4882a593Smuzhiyun } 41*4882a593Smuzhiyun 42