1 /*
2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <asm/io.h>
7 #include <asm/arch/bootrom.h>
8 #include <asm/arch/hardware.h>
9 #include <asm/arch/grf_rk322x.h>
10
11 #define GRF_BASE 0x11000000
12 #define CRU_MISC_CON 0x110e0134
13 #define SGRF_DDR_CON0 0x10150000
14
15 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
16 [BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000",
17 [BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
18 };
19
20 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)21 int arch_cpu_init(void)
22 {
23 static struct rk322x_grf * const grf = (void *)GRF_BASE;
24 /* We do some SoC one time setting here. */
25
26 #ifdef CONFIG_SPL_BUILD
27 /* Disable the ddr secure region setting to make it non-secure */
28 rk_clrreg(SGRF_DDR_CON0, 0x4000);
29 #endif
30
31 /* PWMs select rkpwm clock source */
32 rk_setreg(&grf->soc_con[2], 1 << 0);
33
34 /* PWM0~3 io select */
35 rk_setreg(&grf->con_iomux, 0xf << 0);
36
37 /* UART1~2 io select */
38 rk_setreg(&grf->con_iomux, (1 << 11) | (1 << 8));
39
40 /* HDMI phy clock source select HDMIPHY clock out */
41 rk_clrreg(CRU_MISC_CON, 1 << 13);
42
43 /*
44 * The integrated macphy is enabled by default, disable it
45 * for saving power consuming.
46 */
47 rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK,
48 0 << MACPHY_CFG_ENABLE_SHIFT);
49 /* TODO: ECO version */
50
51 return 0;
52 }
53 #endif
54
board_debug_uart_init(void)55 void board_debug_uart_init(void)
56 {
57 static struct rk322x_grf * const grf = (void *)GRF_BASE;
58 enum {
59 GPIO1B2_SHIFT = 4,
60 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
61 GPIO1B2_GPIO = 0,
62 GPIO1B2_UART21_SIN = 2,
63
64 GPIO1B1_SHIFT = 2,
65 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
66 GPIO1B1_GPIO = 0,
67 GPIO1B1_UART1_SOUT,
68 GPIO1B1_UART21_SOUT,
69 };
70 enum {
71 CON_IOMUX_UART2SEL_SHIFT= 8,
72 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
73 CON_IOMUX_UART2SEL_2 = 0,
74 CON_IOMUX_UART2SEL_21,
75 };
76
77 /* Enable early UART2 channel 1 on the RK322x */
78 rk_clrsetreg(&grf->gpio1b_iomux,
79 GPIO1B1_MASK | GPIO1B2_MASK,
80 GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
81 GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
82 /* Set channel C as UART2 input */
83 rk_clrsetreg(&grf->con_iomux,
84 CON_IOMUX_UART2SEL_MASK,
85 CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
86 }
87