1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2018 Rockchip Electronics Co., Ltd
4 *
5 */
6 #include <common.h>
7 #include <android_image.h>
8 #include <boot_rkimg.h>
9 #include <ramdisk.h>
10 #include <asm/io.h>
11 #include <asm/arch/grf_rk1808.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/rk_atags.h>
14 #include <asm/arch/rockchip_smccc.h>
15 #include <asm/gpio.h>
16 #include <debug_uart.h>
17
18 #include <asm/armv8/mmu.h>
19
20 #define NIU_CIF_ADDR 0xfe8a0188
21 #define NIU_ISP_ADDR 0xfe8a0008
22 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
23
24 static struct mm_region rk1808_mem_map[] = {
25 {
26 .virt = 0x0UL,
27 .phys = 0x0UL,
28 .size = 0xff000000UL,
29 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
30 PTE_BLOCK_INNER_SHARE
31 }, {
32 .virt = 0xf8000000UL,
33 .phys = 0xf8000000UL,
34 .size = 0x08000000UL,
35 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36 PTE_BLOCK_NON_SHARE |
37 PTE_BLOCK_PXN | PTE_BLOCK_UXN
38 }, {
39 /* List terminator */
40 0,
41 }
42 };
43
44 struct mm_region *mem_map = rk1808_mem_map;
45
46 #define GRF_BASE 0xfe000000
47 #define PMUGRF_BASE 0xfe020000
48
49 enum {
50 GPIO4A3_SHIFT = 12,
51 GPIO4A3_MASK = GENMASK(15, 12),
52 GPIO4A3_GPIO = 0,
53 GPIO4A3_SDMMC0_D1,
54 GPIO4A3_UART2_RX_M0,
55
56 GPIO4A2_SHIFT = 8,
57 GPIO4A2_MASK = GENMASK(11, 8),
58 GPIO4A2_GPIO = 0,
59 GPIO4A2_SDMMC0_D0,
60 GPIO4A2_UART2_TX_M0,
61
62 UART2_IO_SEL_SHIFT = 14,
63 UART2_IO_SEL_MASK = GENMASK(15, 14),
64 UART2_IO_SEL_M0 = 0,
65 UART2_IO_SEL_M1,
66 UART2_IO_SEL_M2,
67 UART2_IO_SEL_USB,
68 };
69
70 #define SECURE_FIRE_WALL 0xff590040
71
arch_cpu_init(void)72 int arch_cpu_init(void)
73 {
74 /* Set cif qos priority */
75 writel(QOS_PRIORITY_LEVEL(2, 2), NIU_CIF_ADDR);
76 writel(QOS_PRIORITY_LEVEL(2, 2), NIU_ISP_ADDR);
77
78 /* Set dram to unsecure */
79 #ifdef CONFIG_SPL_BUILD
80 writel(0, SECURE_FIRE_WALL);
81 #endif
82
83 return 0;
84 }
85
86 /*
87 * Default use UART2_TX/RX_M0(TX: GPIO4_A2, RX: GPIO4_A3)
88 */
board_debug_uart_init(void)89 void board_debug_uart_init(void)
90 {
91 #ifdef CONFIG_TPL_BUILD
92 struct rk1808_grf * const grf = (void *)GRF_BASE;
93
94 /* Enable early UART2 channel m0 on the rk1808 */
95 rk_clrsetreg(&grf->iofunc_con0, UART2_IO_SEL_MASK,
96 UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
97
98 /* Switch iomux */
99 rk_clrsetreg(&grf->gpio4a_iomux_l,
100 GPIO4A3_MASK | GPIO4A2_MASK,
101 GPIO4A2_UART2_TX_M0 << GPIO4A2_SHIFT |
102 GPIO4A3_UART2_RX_M0 << GPIO4A3_SHIFT);
103 #endif
104 }
105
106 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_COPROCESSOR_RK1808)
107 #define PINCTRL_EMMC_BUS8_PATH "/pinctrl/emmc/emmc-bus8"
108 #define PINCTRL_EMMC_CMD_PATH "/pinctrl/emmc/emmc-cmd"
109 #define PINCTRL_EMMC_CLK_PATH "/pinctrl/emmc/emmc-clk"
110 #define PINCTRL_PCFG_PU_2MA_PATH "/pinctrl/pcfg-pull-up-2ma"
111 #define MAX_ROCKCHIP_PINS_ENTRIES 12
112
rockchip_pinctrl_cfg_fdt_fixup(const char * path,u32 new_phandle)113 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle)
114 {
115 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
116 const u32 *data;
117 int i, count;
118 int node;
119
120 node = fdt_path_offset(gd->fdt_blob, path);
121 if (node < 0) {
122 debug("%s: can't find: %s\n", __func__, path);
123 return node;
124 }
125
126 data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count);
127 if (!data) {
128 debug("%s: can't find prop \"rockchip,pins\"\n", __func__);
129 return -ENODATA;
130 }
131
132 count /= sizeof(u32);
133 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
134 debug("%s: %d is over max count\n", __func__, count);
135 return -EINVAL;
136 }
137
138 for (i = 0; i < count; i++)
139 cells[i] = data[i];
140
141 for (i = 0; i < (count >> 2); i++)
142 cells[4 * i + 3] = cpu_to_fdt32(new_phandle);
143
144 fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins",
145 &cells, count * sizeof(u32));
146
147 return 0;
148 }
149
rk_board_fdt_fixup(void * blob)150 int rk_board_fdt_fixup(void *blob)
151 {
152 struct tag *t;
153 u32 ph_pu_2ma;
154 int ret = 0;
155
156 t = atags_get_tag(ATAG_SOC_INFO);
157 if (!t)
158 return 0;
159
160 debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags);
161
162 if (t->u.soc.flags != 0x45543030)
163 return 0;
164
165 ph_pu_2ma = fdt_get_phandle(gd->fdt_blob,
166 fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH));
167 if (!ph_pu_2ma) {
168 debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH);
169 return -EINVAL;
170 }
171
172 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma);
173 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma);
174 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma);
175
176 return ret;
177 }
178 #endif
179
180 /*
181 * rockchip: rk1808: fixup "ramdisk_addr_r" by real image address
182 *
183 * We fixup "ramdisk_addr_r" with real image address which has been already
184 * loaded by pre-loader. This brings benefits:
185 *
186 * - It saves boot time when ramdisk is large;
187 * - It avoids memory overlap with original ramdisk data.
188 */
189 #if defined(CONFIG_DM_RAMDISK) && !defined(CONFIG_SPL_BUILD)
env_fixup_ramdisk_addr_r(void)190 static int env_fixup_ramdisk_addr_r(void)
191 {
192 const char *boot_part = PART_BOOT;
193 struct blk_desc *dev_desc;
194 struct andr_img_hdr *hdr;
195 disk_partition_t info;
196 ulong ramdisk_addr_r;
197 int ret;
198
199 /*
200 * Don't rely on CONFIG_DM_RAMDISK since it can be a default
201 * configuration after disk/part_rkram.c was introduced.
202 *
203 * This is compatible code.
204 */
205 if (!dm_ramdisk_is_enabled())
206 return 0;
207
208 dev_desc = rockchip_get_bootdev();
209 if (!dev_desc) {
210 printf("%s: dev_desc is NULL!\n", __func__);
211 return -ENODEV;
212 }
213
214 ret = part_get_info_by_name(dev_desc, boot_part, &info);
215 if (ret < 0) {
216 printf("%s: failed to get %s part, ret=%d\n",
217 __func__, boot_part, ret);
218 }
219
220 hdr = (struct andr_img_hdr *)(info.start * dev_desc->blksz);
221 ramdisk_addr_r = (ulong)hdr;
222 ramdisk_addr_r += hdr->page_size;
223 ramdisk_addr_r += ALIGN(hdr->kernel_size, hdr->page_size);
224 env_set_hex("ramdisk_addr_r", ramdisk_addr_r);
225
226 return 0;
227 }
228 #endif
229
rk_board_init(void)230 int rk_board_init(void)
231 {
232 struct rk1808_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
233
234 /* Set GPIO0_C2 default to pull down from normal */
235 rk_clrsetreg(&pmugrf->gpio0c_p, 0x30, 0x20);
236
237 #if defined(CONFIG_ROCKCHIP_SMCCC) && defined(CONFIG_ROCKCHIP_RK1806)
238 sip_smc_get_sip_version();
239 #endif
240 return 0;
241 }
242
rk_board_late_init(void)243 int rk_board_late_init(void)
244 {
245 #if defined(CONFIG_DM_RAMDISK) && !defined(CONFIG_SPL_BUILD)
246 env_fixup_ramdisk_addr_r();
247 #endif
248
249 return 0;
250 }
251
mmc_gpio_init_direct(void)252 void mmc_gpio_init_direct(void)
253 {
254 struct rk1808_grf * const grf = (void *)GRF_BASE;
255
256 /*
257 * The rk1808's pin drive strength control must set to 2ma.
258 */
259 rk_clrsetreg(&grf->gpio1a_e, 0xffff, 0x5555);
260 rk_clrsetreg(&grf->gpio1b_e, 0xff, 0x00);
261 }
262