1 /*
2 * arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9 #include <common.h>
10 #include <sh_pfc.h>
11 #include <asm/gpio.h>
12
13 #define CPU_32_PORT(fn, pfx, sfx) \
14 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
15 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
16 PORT_1(fn, pfx##31, sfx)
17
18 #define CPU_32_PORT1(fn, pfx, sfx) \
19 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
20 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
21 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
22 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
23
24 /*
25 * GP_0_0_DATA -> GP_7_25_DATA
26 * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
27 * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
28 */
29 #define CPU_ALL_PORT(fn, pfx, sfx) \
30 CPU_32_PORT(fn, pfx##_0_, sfx), \
31 CPU_32_PORT1(fn, pfx##_1_, sfx), \
32 CPU_32_PORT(fn, pfx##_2_, sfx), \
33 CPU_32_PORT(fn, pfx##_3_, sfx), \
34 CPU_32_PORT(fn, pfx##_4_, sfx), \
35 CPU_32_PORT(fn, pfx##_5_, sfx), \
36 CPU_32_PORT(fn, pfx##_6_, sfx), \
37 CPU_32_PORT1(fn, pfx##_7_, sfx)
38
39 #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
40 #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
41 GP##pfx##_IN, GP##pfx##_OUT)
42
43 #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
44 #define _GP_INDT(pfx, sfx) GP##pfx##_DATA
45
46 #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
47 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
48 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
49
50
51 #define PORT_10_REV(fn, pfx, sfx) \
52 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
53 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
54 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
55 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
56 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
57
58 #define CPU_32_PORT_REV(fn, pfx, sfx) \
59 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
60 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
61 PORT_10_REV(fn, pfx, sfx)
62
63 #define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
64 #define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
65
66 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
67 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
68 FN_##ipsr, FN_##fn)
69
70 enum {
71 PINMUX_RESERVED = 0,
72
73 PINMUX_DATA_BEGIN,
74 GP_ALL(DATA),
75 PINMUX_DATA_END,
76
77 PINMUX_INPUT_BEGIN,
78 GP_ALL(IN),
79 PINMUX_INPUT_END,
80
81 PINMUX_OUTPUT_BEGIN,
82 GP_ALL(OUT),
83 PINMUX_OUTPUT_END,
84
85 PINMUX_FUNCTION_BEGIN,
86 GP_ALL(FN),
87
88 /* GPSR0 */
89 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
90 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
91 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
92 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
93 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
94 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
95
96 /* GPSR1 */
97 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
98 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
99 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
100 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
101 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
102 FN_IP3_21_20,
103
104 /* GPSR2 */
105 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
106 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
107 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
108 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
109 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
110 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
111 FN_IP6_5_3, FN_IP6_7_6,
112
113 /* GPSR3 */
114 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
115 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
116 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
117 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
118 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
119 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
120 FN_IP9_18_17,
121
122 /* GPSR4 */
123 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
124 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
125 FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
126 FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
127 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
128 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
129 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
130 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
131
132 /* GPSR5 */
133 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
134 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
135 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
136 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
137 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
138 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
139 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
140
141 /* GPSR6 */
142 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
143 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
144 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
145 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
146 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
147 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
148
149 /* GPSR7 */
150 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
151 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
152 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
153 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
154 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
155 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
156
157 /* IPSR 0 -5 */
158
159 /* IPSR6 */
160 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
161 FN_SCIF_CLK, FN_BPFCLK_E,
162 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
163 FN_SCIFA2_RXD, FN_FMIN_E,
164 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
165 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
166 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
167 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
168 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
169 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
170 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
171 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
172 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
173 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
174
175 /* IPSR7 - IPSR10 */
176
177 /* IPSR11 */
178 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
179 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
180 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
181 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
182 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
183 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
184 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
185 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
186 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
187 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
188 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
189 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
190 FN_VI1_DATA7, FN_AVB_MDC,
191 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
192 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
193
194 /* IPSR12 */
195 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
196 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
197 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
198 FN_SCL2_D, FN_MSIOF1_RXD_E,
199 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
200 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
201 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
202 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
203 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
204 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
205 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
206 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
207 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
208 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
209 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
210 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
211 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
212
213 /* IPSR13 */
214 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
215 FN_ADICLK_B, FN_MSIOF0_SS1_C,
216 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
217 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
218 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
219 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
220 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
221 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
222 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
223 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
224 FN_SCIFA5_TXD_B, FN_TX3_C,
225 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
226 FN_SCIFA5_RXD_B, FN_RX3_C,
227 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
228 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
229 FN_SD1_DATA3, FN_IERX_B,
230 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
231
232 /* IPSR14 */
233 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
234 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
235 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
236 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
237 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
238 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
239 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
240 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
241 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
242 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
243 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
244 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
245 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
246 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
247
248 /* IPSR15 */
249 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
250 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
251 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
252 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
253 FN_PWM5_B, FN_SCIFA3_TXD_C,
254 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
255 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
256 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
257 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
258 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
259 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
260 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
261 FN_TCLK2, FN_VI1_DATA3_C,
262 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
263 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
264
265 /* IPSR16 */
266 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
267 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
268 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
269 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
270 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
271
272 /* MOD_SEL */
273 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
274 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
275 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
276 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
277 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
278 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
279 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
280 FN_SEL_QSP_0, FN_SEL_QSP_1,
281 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
282 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
283 FN_SEL_HSCIF1_4,
284 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
285 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
286 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
287 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
288 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
289
290 /* MOD_SEL2 */
291 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
292 FN_SEL_SCIF0_4,
293 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
294 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
295 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
296 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
297 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
298 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
299 FN_SEL_ADG_0, FN_SEL_ADG_1,
300 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
301 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
302 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
303 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
304 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
305 FN_SEL_SIM_0, FN_SEL_SIM_1,
306 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
307
308 /* MOD_SEL3 */
309 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
310 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
311 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
312 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
313 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
314 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
315 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
316 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
317 FN_SEL_MMC_0, FN_SEL_MMC_1,
318 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
319 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
320 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
321 FN_SEL_IIC1_4,
322 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
323
324 /* MOD_SEL4 */
325 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
326 FN_SEL_SOF1_4,
327 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
328 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
329 FN_SEL_RAD_0, FN_SEL_RAD_1,
330 FN_SEL_RCN_0, FN_SEL_RCN_1,
331 FN_SEL_RSP_0, FN_SEL_RSP_1,
332 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
333 FN_SEL_SCIF2_4,
334 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
335 FN_SEL_SOF2_4,
336 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
337 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
338 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
339 PINMUX_FUNCTION_END,
340
341 PINMUX_MARK_BEGIN,
342
343 EX_CS0_N_MARK, RD_N_MARK,
344
345 AUDIO_CLKA_MARK,
346
347 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
348 VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
349 VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
350
351 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
352
353 /* IPSR0 - 5 */
354
355 /* IPSR6 */
356 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
357 SCIF_CLK_MARK, BPFCLK_E_MARK,
358 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
359 SCIFA2_RXD_MARK, FMIN_E_MARK,
360 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
361 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
362 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
363 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
364 IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
365 IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
366 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
367 IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
368 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
369 SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
370 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
371 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
372 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
373 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
374
375 /* IPSR7 - 10 */
376
377 /* IPSR11 */
378 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
379 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
380 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
381 SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
382 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
383 TX4_B_MARK, SCIFA4_TXD_B_MARK,
384 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
385 RX4_B_MARK, SCIFA4_RXD_B_MARK,
386 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
387 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
388 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
389 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
390 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
391 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
392 VI1_DATA7_MARK, AVB_MDC_MARK,
393 ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
394 ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
395
396 /* IPSR12 */
397 ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
398 ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
399 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
400 SCL2_D_MARK, MSIOF1_RXD_E_MARK,
401 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
402 SDA2_D_MARK, MSIOF1_SCK_E_MARK,
403 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
404 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
405 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
406 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
407 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
408 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
409 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
410 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
411 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
412 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
413 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
414 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
415
416 /* IPSR13 */
417 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
418 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
419 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
420 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
421 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
422 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
423 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
424 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
425 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
426 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
427 SCIFA5_TXD_B_MARK, TX3_C_MARK,
428 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
429 SCIFA5_RXD_B_MARK, RX3_C_MARK,
430 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
431 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
432 SD1_DATA3_MARK, IERX_B_MARK,
433 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
434
435 /* IPSR14 */
436 SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
437 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
438 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
439 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
440 SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
441 SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
442 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
443 VI1_CLK_C_MARK, VI1_G0_B_MARK,
444 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
445 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
446 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
447 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
448 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
449 VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
450 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
451 VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
452
453 /* IPSR15 */
454 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
455 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
456 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
457 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
458 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
459 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
460 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
461 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
462 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
463 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
464 TCLK1_MARK, VI1_DATA1_C_MARK,
465 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
466 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
467 TCLK2_MARK, VI1_DATA3_C_MARK,
468 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
469 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
470 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
471 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
472
473 /* IPSR16 */
474 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
475 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
476 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
477 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
478 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
479 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
480 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
481 PINMUX_MARK_END,
482 };
483
484 static pinmux_enum_t pinmux_data[] = {
485 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
486
487 PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
488 PINMUX_DATA(RD_N_MARK, FN_RD_N),
489 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
490 PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
491 PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
492 PINMUX_DATA(VI0_DATA0_VI0_B1_MARK, FN_VI0_DATA0_VI0_B1),
493 PINMUX_DATA(VI0_DATA0_VI0_B2_MARK, FN_VI0_DATA0_VI0_B2),
494 PINMUX_DATA(VI0_DATA0_VI0_B4_MARK, FN_VI0_DATA0_VI0_B4),
495 PINMUX_DATA(VI0_DATA0_VI0_B5_MARK, FN_VI0_DATA0_VI0_B5),
496 PINMUX_DATA(VI0_DATA0_VI0_B6_MARK, FN_VI0_DATA0_VI0_B6),
497 PINMUX_DATA(VI0_DATA0_VI0_B7_MARK, FN_VI0_DATA0_VI0_B7),
498 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
499 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
500 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
501
502 /* IPSR0 - 5 */
503
504 /* IPSR6 */
505 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
506 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
507 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
508 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
509 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
510 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
511 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
512 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
513 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
514 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
515 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
516 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
517 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
518 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
519 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
520 PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
521 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
522 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
523 PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
524 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
525 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
526 PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
527 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
528 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
529 PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
530 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
531 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
532 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
533 PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
534 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
535 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
536 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
537 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
538 PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
539 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
540 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
541 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
542 PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
543 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
544 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
545 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
546 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
547 PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
548 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
549 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
550 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
551 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
552 PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
553 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
554 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
555 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
556 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
557
558 /* IPSR7 - 10 */
559
560 /* IPSR11 */
561 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
562 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
563 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
564 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
565 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
566 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
567 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
568 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
569 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
570 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
571 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
572 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
573 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
574 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
575 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
576 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
577 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
578 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
579 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
580 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
581 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
582 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
583 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
584 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
585 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
586 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
587 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
588 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
589 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
590 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
591 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
592 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
593 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
594 PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
595 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
596 PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
597 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
598 PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
599 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
600 PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
601 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
602 PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
603 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
604 PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
605 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
606 PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
607 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
608 PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
609 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
610 PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
611 PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
612 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
613 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
614 PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
615 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
616 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
617 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
618
619 /* IPSR12 */
620 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
621 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
622 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
623 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
624 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
625 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
626 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
627 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
628 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
629 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
630 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
631 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
632 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
633 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
634 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
635 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
636 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
637 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
638 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
639 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
640 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
641 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
642 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
643 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
644 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
645 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
646 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
647 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
648 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
649 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
650 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
651 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
652 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
653 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
654 PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
655 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
656 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
657 PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
658 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
659 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
660 PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
661 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
662 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
663 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
664 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
665 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
666 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
667 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
668 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
669 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
670 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
671
672 /* IPSR13 */
673 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
674 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
675 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
676 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
677 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
678 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
679 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
680 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
681 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
682 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
683 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
684 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
685 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
686 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
687 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
688 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
689 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
690 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
691 PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
692 PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
693 PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
694 PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
695 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
696 PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
697 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
698 PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
699 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
700 PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
701 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
702 PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
703 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
704 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
705 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
706 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
707 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
708 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
709 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
710 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
711 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
712 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
713 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
714 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
715 PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
716 PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
717 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
718 PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
719 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
720 PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
721 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
722 PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
723 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
724 PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
725 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
726 PINMUX_IPSR_DATA(IP13_30_28, PWM0),
727 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
728 PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
729
730 /* IPSR14 */
731 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
732 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
733 PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
734 PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
735 PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
736 PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
737 PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
738 PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
739 PINMUX_IPSR_DATA(IP14_4, MMC_D0),
740 PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
741 PINMUX_IPSR_DATA(IP14_5, MMC_D1),
742 PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
743 PINMUX_IPSR_DATA(IP14_6, MMC_D2),
744 PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
745 PINMUX_IPSR_DATA(IP14_7, MMC_D3),
746 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
747 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
748 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
749 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
750 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
751 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
752 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
753 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
754 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
755 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
756 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
757 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
758 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
759 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
760 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
761 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
762 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
763 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
764 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
765 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
766 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
767 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
768 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
769 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
770 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
771 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
772 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
773 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
774 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
775 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
776 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
777 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
778 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
779 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
780 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
781 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
782 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
783 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
784 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
785 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
786 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
787 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
788
789 /* IPSR15 */
790 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
791 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
792 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
793 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
794 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
795 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
796 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
797 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
798 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
799 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
800 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
801 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
802 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
803 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
804 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
805 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
806 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
807 PINMUX_IPSR_DATA(IP15_11_9, PWM5),
808 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
809 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
810 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
811 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
812 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
813 PINMUX_IPSR_DATA(IP15_14_12, PWM6),
814 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
815 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
816 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
817 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
818 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
819 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
820 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
821 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
822 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
823 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
824 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
825 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
826 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
827 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
828 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
829 PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
830 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
831 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
832 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
833 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
834 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
835 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
836 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
837 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
838 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
839 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
840 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
841
842 /* IPSR16 */
843 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
844 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
845 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
846 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
847 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
848 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
849 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
850 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
851 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
852 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
853 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
854 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
855 PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
856 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
857 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
858 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
859 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
860 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
861 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
862 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
863 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
864 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
865 };
866
867 static struct pinmux_gpio pinmux_gpios[] = {
868 PINMUX_GPIO_GP_ALL(),
869
870 GPIO_FN(EX_CS0_N), GPIO_FN(RD_N), GPIO_FN(AUDIO_CLKA),
871 GPIO_FN(VI0_CLK), GPIO_FN(VI0_DATA0_VI0_B0),
872 GPIO_FN(VI0_DATA0_VI0_B1), GPIO_FN(VI0_DATA0_VI0_B2),
873 GPIO_FN(VI0_DATA0_VI0_B4), GPIO_FN(VI0_DATA0_VI0_B5),
874 GPIO_FN(VI0_DATA0_VI0_B6), GPIO_FN(VI0_DATA0_VI0_B7),
875 GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
876
877 /* IPSR0 - 5 */
878
879 /* IPSR6 */
880 GPIO_FN(AUDIO_CLKB), GPIO_FN(STP_OPWM_0_B), GPIO_FN(MSIOF1_SCK_B),
881 GPIO_FN(SCIF_CLK), GPIO_FN(BPFCLK_E),
882 GPIO_FN(AUDIO_CLKC), GPIO_FN(SCIFB0_SCK_C),
883 GPIO_FN(MSIOF1_SYNC_B), GPIO_FN(RX2),
884 GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN_E),
885 GPIO_FN(AUDIO_CLKOUT), GPIO_FN(MSIOF1_SS1_B),
886 GPIO_FN(TX2), GPIO_FN(SCIFA2_TXD),
887 GPIO_FN(IRQ0), GPIO_FN(SCIFB1_RXD_D), GPIO_FN(INTC_IRQ0_N),
888 GPIO_FN(IRQ1), GPIO_FN(SCIFB1_SCK_C), GPIO_FN(INTC_IRQ1_N),
889 GPIO_FN(IRQ2), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(INTC_IRQ2_N),
890 GPIO_FN(IRQ3), GPIO_FN(SCL4_C),
891 GPIO_FN(MSIOF2_TXD_E), GPIO_FN(INTC_IRQ3_N),
892 GPIO_FN(IRQ4), GPIO_FN(HRX1_C), GPIO_FN(SDA4_C),
893 GPIO_FN(MSIOF2_RXD_E), GPIO_FN(INTC_IRQ4_N),
894 GPIO_FN(IRQ5), GPIO_FN(HTX1_C), GPIO_FN(SCL1_E), GPIO_FN(MSIOF2_SCK_E),
895 GPIO_FN(IRQ6), GPIO_FN(HSCK1_C), GPIO_FN(MSIOF1_SS2_B),
896 GPIO_FN(SDA1_E), GPIO_FN(MSIOF2_SYNC_E),
897 GPIO_FN(IRQ7), GPIO_FN(HCTS1_N_C), GPIO_FN(MSIOF1_TXD_B),
898 GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D),
899 GPIO_FN(IRQ8), GPIO_FN(HRTS1_N_C), GPIO_FN(MSIOF1_RXD_B),
900 GPIO_FN(GPS_SIGN_C), GPIO_FN(GPS_SIGN_D),
901
902 /* IPSR7 - 10 */
903
904 /* IPSR11 */
905 GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
906 GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
907 GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
908 GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
909 GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
910 GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
911 GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
912 GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
913 GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
914 GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
915 GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
916 GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
917 GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
918 GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
919 GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
920 GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
921 GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
922 GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
923 GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
924 GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
925 GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
926 GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
927 GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
928 GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
929
930 /* IPSR12 */
931 GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
932 GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
933 GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
934 GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
935 GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
936 GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
937 GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
938 GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
939 GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
940 GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
941 GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
942 GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
943 GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
944 GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
945 GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
946 GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
947 GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
948 GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
949 GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
950
951 /* IPSR13 */
952 GPIO_FN(STP_ISD_0), GPIO_FN(AVB_TX_ER), GPIO_FN(SCIFB2_SCK_C),
953 GPIO_FN(ADICLK_B), GPIO_FN(MSIOF0_SS1_C),
954 GPIO_FN(STP_ISEN_0), GPIO_FN(AVB_TX_CLK),
955 GPIO_FN(ADICHS0_B), GPIO_FN(MSIOF0_SS2_C),
956 GPIO_FN(STP_ISSYNC_0), GPIO_FN(AVB_COL),
957 GPIO_FN(ADICHS1_B), GPIO_FN(MSIOF0_RXD_C),
958 GPIO_FN(STP_OPWM_0), GPIO_FN(AVB_GTX_CLK), GPIO_FN(PWM0_B),
959 GPIO_FN(ADICHS2_B), GPIO_FN(MSIOF0_TXD_C),
960 GPIO_FN(SD0_CLK), GPIO_FN(SPCLK_B),
961 GPIO_FN(SD0_CMD), GPIO_FN(MOSI_IO0_B),
962 GPIO_FN(SD0_DATA0), GPIO_FN(MISO_IO1_B),
963 GPIO_FN(SD0_DATA1), GPIO_FN(IO2_B),
964 GPIO_FN(SD0_DATA2), GPIO_FN(IO3_B), GPIO_FN(SD0_DATA3), GPIO_FN(SSL_B),
965 GPIO_FN(SD0_CD), GPIO_FN(MMC_D6_B),
966 GPIO_FN(SIM0_RST_B), GPIO_FN(CAN0_RX_F),
967 GPIO_FN(SCIFA5_TXD_B), GPIO_FN(TX3_C),
968 GPIO_FN(SD0_WP), GPIO_FN(MMC_D7_B),
969 GPIO_FN(SIM0_D_B), GPIO_FN(CAN0_TX_F),
970 GPIO_FN(SCIFA5_RXD_B), GPIO_FN(RX3_C),
971 GPIO_FN(SD1_CMD), GPIO_FN(REMOCON_B),
972 GPIO_FN(SD1_DATA0), GPIO_FN(SPEEDIN_B),
973 GPIO_FN(SD1_DATA1), GPIO_FN(IETX_B),
974 GPIO_FN(SD1_DATA2), GPIO_FN(IECLK_B),
975 GPIO_FN(SD1_DATA3), GPIO_FN(IERX_B),
976 GPIO_FN(SD1_CD), GPIO_FN(PWM0), GPIO_FN(TPU_TO0), GPIO_FN(SCL1_C),
977
978 /* IPSR14 */
979 GPIO_FN(SD1_WP), GPIO_FN(PWM1_B), GPIO_FN(SDA1_C),
980 GPIO_FN(SD2_CLK), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CMD), GPIO_FN(MMC_CMD),
981 GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D0),
982 GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D1),
983 GPIO_FN(SD2_DATA2), GPIO_FN(MMC_D2),
984 GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D3),
985 GPIO_FN(SD2_CD), GPIO_FN(MMC_D4), GPIO_FN(SCL8_C),
986 GPIO_FN(TX5_B), GPIO_FN(SCIFA5_TXD_C),
987 GPIO_FN(SD2_WP), GPIO_FN(MMC_D5), GPIO_FN(SDA8_C),
988 GPIO_FN(RX5_B), GPIO_FN(SCIFA5_RXD_C),
989 GPIO_FN(MSIOF0_SCK), GPIO_FN(RX2_C), GPIO_FN(ADIDATA),
990 GPIO_FN(VI1_CLK_C), GPIO_FN(VI1_G0_B),
991 GPIO_FN(MSIOF0_SYNC), GPIO_FN(TX2_C), GPIO_FN(ADICS_SAMP),
992 GPIO_FN(VI1_CLKENB_C), GPIO_FN(VI1_G1_B),
993 GPIO_FN(MSIOF0_TXD), GPIO_FN(ADICLK),
994 GPIO_FN(VI1_FIELD_C), GPIO_FN(VI1_G2_B),
995 GPIO_FN(MSIOF0_RXD), GPIO_FN(ADICHS0),
996 GPIO_FN(VI1_DATA0_C), GPIO_FN(VI1_G3_B),
997 GPIO_FN(MSIOF0_SS1), GPIO_FN(MMC_D6), GPIO_FN(ADICHS1), GPIO_FN(TX0_E),
998 GPIO_FN(VI1_HSYNC_N_C), GPIO_FN(SCL7_C), GPIO_FN(VI1_G4_B),
999 GPIO_FN(MSIOF0_SS2), GPIO_FN(MMC_D7), GPIO_FN(ADICHS2), GPIO_FN(RX0_E),
1000 GPIO_FN(VI1_VSYNC_N_C), GPIO_FN(SDA7_C), GPIO_FN(VI1_G5_B),
1001
1002 /* IPSR15 */
1003 GPIO_FN(SIM0_RST), GPIO_FN(IETX), GPIO_FN(CAN1_TX_D),
1004 GPIO_FN(SIM0_CLK), GPIO_FN(IECLK), GPIO_FN(CAN_CLK_C),
1005 GPIO_FN(SIM0_D), GPIO_FN(IERX), GPIO_FN(CAN1_RX_D),
1006 GPIO_FN(GPS_CLK), GPIO_FN(DU1_DOTCLKIN_C), GPIO_FN(AUDIO_CLKB_B),
1007 GPIO_FN(PWM5_B), GPIO_FN(SCIFA3_TXD_C),
1008 GPIO_FN(GPS_SIGN), GPIO_FN(TX4_C),
1009 GPIO_FN(SCIFA4_TXD_C), GPIO_FN(PWM5),
1010 GPIO_FN(VI1_G6_B), GPIO_FN(SCIFA3_RXD_C),
1011 GPIO_FN(GPS_MAG), GPIO_FN(RX4_C), GPIO_FN(SCIFA4_RXD_C), GPIO_FN(PWM6),
1012 GPIO_FN(VI1_G7_B), GPIO_FN(SCIFA3_SCK_C),
1013 GPIO_FN(HCTS0_N), GPIO_FN(SCIFB0_CTS_N), GPIO_FN(GLO_I0_C),
1014 GPIO_FN(TCLK1), GPIO_FN(VI1_DATA1_C),
1015 GPIO_FN(HRTS0_N), GPIO_FN(SCIFB0_RTS_N),
1016 GPIO_FN(GLO_I1_C), GPIO_FN(VI1_DATA2_C),
1017 GPIO_FN(HSCK0), GPIO_FN(SCIFB0_SCK),
1018 GPIO_FN(GLO_Q0_C), GPIO_FN(CAN_CLK),
1019 GPIO_FN(TCLK2), GPIO_FN(VI1_DATA3_C),
1020 GPIO_FN(HRX0), GPIO_FN(SCIFB0_RXD), GPIO_FN(GLO_Q1_C),
1021 GPIO_FN(CAN0_RX_B), GPIO_FN(VI1_DATA4_C),
1022 GPIO_FN(HTX0), GPIO_FN(SCIFB0_TXD), GPIO_FN(GLO_SCLK_C),
1023 GPIO_FN(CAN0_TX_B), GPIO_FN(VI1_DATA5_C),
1024
1025 /* IPSR16 */
1026 GPIO_FN(HRX1), GPIO_FN(SCIFB1_RXD), GPIO_FN(VI1_R0_B),
1027 GPIO_FN(GLO_SDATA_C), GPIO_FN(VI1_DATA6_C),
1028 GPIO_FN(HTX1), GPIO_FN(SCIFB1_TXD), GPIO_FN(VI1_R1_B),
1029 GPIO_FN(GLO_SS_C), GPIO_FN(VI1_DATA7_C),
1030 GPIO_FN(HSCK1), GPIO_FN(SCIFB1_SCK),
1031 GPIO_FN(MLB_CK), GPIO_FN(GLO_RFON_C),
1032 GPIO_FN(HCTS1_N), GPIO_FN(SCIFB1_CTS_N),
1033 GPIO_FN(MLB_SIG), GPIO_FN(CAN1_TX_B),
1034 GPIO_FN(HRTS1_N), GPIO_FN(SCIFB1_RTS_N),
1035 GPIO_FN(MLB_DAT), GPIO_FN(CAN1_RX_B),
1036 };
1037
1038 static struct pinmux_cfg_reg pinmux_config_regs[] = {
1039 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1040 GP_0_31_FN, FN_IP1_22_20,
1041 GP_0_30_FN, FN_IP1_19_17,
1042 GP_0_29_FN, FN_IP1_16_14,
1043 GP_0_28_FN, FN_IP1_13_11,
1044 GP_0_27_FN, FN_IP1_10_8,
1045 GP_0_26_FN, FN_IP1_7_6,
1046 GP_0_25_FN, FN_IP1_5_4,
1047 GP_0_24_FN, FN_IP1_3_2,
1048 GP_0_23_FN, FN_IP1_1_0,
1049 GP_0_22_FN, FN_IP0_30_29,
1050 GP_0_21_FN, FN_IP0_28_27,
1051 GP_0_20_FN, FN_IP0_26_25,
1052 GP_0_19_FN, FN_IP0_24_23,
1053 GP_0_18_FN, FN_IP0_22_21,
1054 GP_0_17_FN, FN_IP0_20_19,
1055 GP_0_16_FN, FN_IP0_18_16,
1056 GP_0_15_FN, FN_IP0_15,
1057 GP_0_14_FN, FN_IP0_14,
1058 GP_0_13_FN, FN_IP0_13,
1059 GP_0_12_FN, FN_IP0_12,
1060 GP_0_11_FN, FN_IP0_11,
1061 GP_0_10_FN, FN_IP0_10,
1062 GP_0_9_FN, FN_IP0_9,
1063 GP_0_8_FN, FN_IP0_8,
1064 GP_0_7_FN, FN_IP0_7,
1065 GP_0_6_FN, FN_IP0_6,
1066 GP_0_5_FN, FN_IP0_5,
1067 GP_0_4_FN, FN_IP0_4,
1068 GP_0_3_FN, FN_IP0_3,
1069 GP_0_2_FN, FN_IP0_2,
1070 GP_0_1_FN, FN_IP0_1,
1071 GP_0_0_FN, FN_IP0_0, }
1072 },
1073 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1074 0, 0,
1075 0, 0,
1076 0, 0,
1077 0, 0,
1078 0, 0,
1079 0, 0,
1080 GP_1_25_FN, FN_IP3_21_20,
1081 GP_1_24_FN, FN_IP3_19_18,
1082 GP_1_23_FN, FN_IP3_17_16,
1083 GP_1_22_FN, FN_IP3_15_14,
1084 GP_1_21_FN, FN_IP3_13_12,
1085 GP_1_20_FN, FN_IP3_11_9,
1086 GP_1_19_FN, FN_RD_N,
1087 GP_1_18_FN, FN_IP3_8_6,
1088 GP_1_17_FN, FN_IP3_5_3,
1089 GP_1_16_FN, FN_IP3_2_0,
1090 GP_1_15_FN, FN_IP2_29_27,
1091 GP_1_14_FN, FN_IP2_26_25,
1092 GP_1_13_FN, FN_IP2_24_23,
1093 GP_1_12_FN, FN_EX_CS0_N,
1094 GP_1_11_FN, FN_IP2_22_21,
1095 GP_1_10_FN, FN_IP2_20_19,
1096 GP_1_9_FN, FN_IP2_18_16,
1097 GP_1_8_FN, FN_IP2_15_13,
1098 GP_1_7_FN, FN_IP2_12_10,
1099 GP_1_6_FN, FN_IP2_9_7,
1100 GP_1_5_FN, FN_IP2_6_5,
1101 GP_1_4_FN, FN_IP2_4_3,
1102 GP_1_3_FN, FN_IP2_2_0,
1103 GP_1_2_FN, FN_IP1_31_29,
1104 GP_1_1_FN, FN_IP1_28_26,
1105 GP_1_0_FN, FN_IP1_25_23, }
1106 },
1107 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1108 GP_2_31_FN, FN_IP6_7_6,
1109 GP_2_30_FN, FN_IP6_5_3,
1110 GP_2_29_FN, FN_IP6_2_0,
1111 GP_2_28_FN, FN_AUDIO_CLKA,
1112 GP_2_27_FN, FN_IP5_31_29,
1113 GP_2_26_FN, FN_IP5_28_26,
1114 GP_2_25_FN, FN_IP5_25_24,
1115 GP_2_24_FN, FN_IP5_23_22,
1116 GP_2_23_FN, FN_IP5_21_20,
1117 GP_2_22_FN, FN_IP5_19_17,
1118 GP_2_21_FN, FN_IP5_16_15,
1119 GP_2_20_FN, FN_IP5_14_12,
1120 GP_2_19_FN, FN_IP5_11_9,
1121 GP_2_18_FN, FN_IP5_8_6,
1122 GP_2_17_FN, FN_IP5_5_3,
1123 GP_2_16_FN, FN_IP5_2_0,
1124 GP_2_15_FN, FN_IP4_30_28,
1125 GP_2_14_FN, FN_IP4_27_26,
1126 GP_2_13_FN, FN_IP4_25_24,
1127 GP_2_12_FN, FN_IP4_23_22,
1128 GP_2_11_FN, FN_IP4_21,
1129 GP_2_10_FN, FN_IP4_20,
1130 GP_2_9_FN, FN_IP4_19,
1131 GP_2_8_FN, FN_IP4_18_16,
1132 GP_2_7_FN, FN_IP4_15_13,
1133 GP_2_6_FN, FN_IP4_12_10,
1134 GP_2_5_FN, FN_IP4_9_8,
1135 GP_2_4_FN, FN_IP4_7_5,
1136 GP_2_3_FN, FN_IP4_4_2,
1137 GP_2_2_FN, FN_IP4_1_0,
1138 GP_2_1_FN, FN_IP3_30_28,
1139 GP_2_0_FN, FN_IP3_27_25 }
1140 },
1141 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1142 GP_3_31_FN, FN_IP9_18_17,
1143 GP_3_30_FN, FN_IP9_16,
1144 GP_3_29_FN, FN_IP9_15_13,
1145 GP_3_28_FN, FN_IP9_12,
1146 GP_3_27_FN, FN_IP9_11,
1147 GP_3_26_FN, FN_IP9_10_8,
1148 GP_3_25_FN, FN_IP9_7,
1149 GP_3_24_FN, FN_IP9_6,
1150 GP_3_23_FN, FN_IP9_5_3,
1151 GP_3_22_FN, FN_IP9_2_0,
1152 GP_3_21_FN, FN_IP8_30_28,
1153 GP_3_20_FN, FN_IP8_27_26,
1154 GP_3_19_FN, FN_IP8_25_24,
1155 GP_3_18_FN, FN_IP8_23_21,
1156 GP_3_17_FN, FN_IP8_20_18,
1157 GP_3_16_FN, FN_IP8_17_15,
1158 GP_3_15_FN, FN_IP8_14_12,
1159 GP_3_14_FN, FN_IP8_11_9,
1160 GP_3_13_FN, FN_IP8_8_6,
1161 GP_3_12_FN, FN_IP8_5_3,
1162 GP_3_11_FN, FN_IP8_2_0,
1163 GP_3_10_FN, FN_IP7_29_27,
1164 GP_3_9_FN, FN_IP7_26_24,
1165 GP_3_8_FN, FN_IP7_23_21,
1166 GP_3_7_FN, FN_IP7_20_19,
1167 GP_3_6_FN, FN_IP7_18_17,
1168 GP_3_5_FN, FN_IP7_16_15,
1169 GP_3_4_FN, FN_IP7_14_13,
1170 GP_3_3_FN, FN_IP7_12_11,
1171 GP_3_2_FN, FN_IP7_10_9,
1172 GP_3_1_FN, FN_IP7_8_6,
1173 GP_3_0_FN, FN_IP7_5_3 }
1174 },
1175 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1176 GP_4_31_FN, FN_IP15_5_4,
1177 GP_4_30_FN, FN_IP15_3_2,
1178 GP_4_29_FN, FN_IP15_1_0,
1179 GP_4_28_FN, FN_IP11_8_6,
1180 GP_4_27_FN, FN_IP11_5_3,
1181 GP_4_26_FN, FN_IP11_2_0,
1182 GP_4_25_FN, FN_IP10_31_29,
1183 GP_4_24_FN, FN_IP10_28_27,
1184 GP_4_23_FN, FN_IP10_26_25,
1185 GP_4_22_FN, FN_IP10_24_22,
1186 GP_4_21_FN, FN_IP10_21_19,
1187 GP_4_20_FN, FN_IP10_18_17,
1188 GP_4_19_FN, FN_IP10_16_15,
1189 GP_4_18_FN, FN_IP10_14_12,
1190 GP_4_17_FN, FN_IP10_11_9,
1191 GP_4_16_FN, FN_IP10_8_6,
1192 GP_4_15_FN, FN_IP10_5_3,
1193 GP_4_14_FN, FN_IP10_2_0,
1194 GP_4_13_FN, FN_IP9_31_29,
1195 GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
1196 GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
1197 GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
1198 GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
1199 GP_4_8_FN, FN_IP9_28_27,
1200 GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
1201 GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
1202 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
1203 GP_4_4_FN, FN_IP9_26_25,
1204 GP_4_3_FN, FN_IP9_24_23,
1205 GP_4_2_FN, FN_IP9_22_21,
1206 GP_4_1_FN, FN_IP9_20_19,
1207 GP_4_0_FN, FN_VI0_CLK }
1208 },
1209 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1210 GP_5_31_FN, FN_IP3_24_22,
1211 GP_5_30_FN, FN_IP13_9_7,
1212 GP_5_29_FN, FN_IP13_6_5,
1213 GP_5_28_FN, FN_IP13_4_3,
1214 GP_5_27_FN, FN_IP13_2_0,
1215 GP_5_26_FN, FN_IP12_29_27,
1216 GP_5_25_FN, FN_IP12_26_24,
1217 GP_5_24_FN, FN_IP12_23_22,
1218 GP_5_23_FN, FN_IP12_21_20,
1219 GP_5_22_FN, FN_IP12_19_18,
1220 GP_5_21_FN, FN_IP12_17_16,
1221 GP_5_20_FN, FN_IP12_15_13,
1222 GP_5_19_FN, FN_IP12_12_10,
1223 GP_5_18_FN, FN_IP12_9_7,
1224 GP_5_17_FN, FN_IP12_6_4,
1225 GP_5_16_FN, FN_IP12_3_2,
1226 GP_5_15_FN, FN_IP12_1_0,
1227 GP_5_14_FN, FN_IP11_31_30,
1228 GP_5_13_FN, FN_IP11_29_28,
1229 GP_5_12_FN, FN_IP11_27,
1230 GP_5_11_FN, FN_IP11_26,
1231 GP_5_10_FN, FN_IP11_25,
1232 GP_5_9_FN, FN_IP11_24,
1233 GP_5_8_FN, FN_IP11_23,
1234 GP_5_7_FN, FN_IP11_22,
1235 GP_5_6_FN, FN_IP11_21,
1236 GP_5_5_FN, FN_IP11_20,
1237 GP_5_4_FN, FN_IP11_19,
1238 GP_5_3_FN, FN_IP11_18_17,
1239 GP_5_2_FN, FN_IP11_16_15,
1240 GP_5_1_FN, FN_IP11_14_12,
1241 GP_5_0_FN, FN_IP11_11_9 }
1242 },
1243 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
1244 0, 0,
1245 0, 0,
1246 GP_6_29_FN, FN_IP14_31_29,
1247 GP_6_28_FN, FN_IP14_28_26,
1248 GP_6_27_FN, FN_IP14_25_23,
1249 GP_6_26_FN, FN_IP14_22_20,
1250 GP_6_25_FN, FN_IP14_19_17,
1251 GP_6_24_FN, FN_IP14_16_14,
1252 GP_6_23_FN, FN_IP14_13_11,
1253 GP_6_22_FN, FN_IP14_10_8,
1254 GP_6_21_FN, FN_IP14_7,
1255 GP_6_20_FN, FN_IP14_6,
1256 GP_6_19_FN, FN_IP14_5,
1257 GP_6_18_FN, FN_IP14_4,
1258 GP_6_17_FN, FN_IP14_3,
1259 GP_6_16_FN, FN_IP14_2,
1260 GP_6_15_FN, FN_IP14_1_0,
1261 GP_6_14_FN, FN_IP13_30_28,
1262 GP_6_13_FN, FN_IP13_27,
1263 GP_6_12_FN, FN_IP13_26,
1264 GP_6_11_FN, FN_IP13_25,
1265 GP_6_10_FN, FN_IP13_24_23,
1266 GP_6_9_FN, FN_IP13_22,
1267 0, 0,
1268 GP_6_7_FN, FN_IP13_21_19,
1269 GP_6_6_FN, FN_IP13_18_16,
1270 GP_6_5_FN, FN_IP13_15,
1271 GP_6_4_FN, FN_IP13_14,
1272 GP_6_3_FN, FN_IP13_13,
1273 GP_6_2_FN, FN_IP13_12,
1274 GP_6_1_FN, FN_IP13_11,
1275 GP_6_0_FN, FN_IP13_10 }
1276 },
1277 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
1278 0, 0,
1279 0, 0,
1280 0, 0,
1281 0, 0,
1282 0, 0,
1283 0, 0,
1284 GP_7_25_FN, FN_USB1_PWEN,
1285 GP_7_24_FN, FN_USB0_OVC,
1286 GP_7_23_FN, FN_USB0_PWEN,
1287 GP_7_22_FN, FN_IP15_14_12,
1288 GP_7_21_FN, FN_IP15_11_9,
1289 GP_7_20_FN, FN_IP15_8_6,
1290 GP_7_19_FN, FN_IP7_2_0,
1291 GP_7_18_FN, FN_IP6_29_27,
1292 GP_7_17_FN, FN_IP6_26_24,
1293 GP_7_16_FN, FN_IP6_23_21,
1294 GP_7_15_FN, FN_IP6_20_19,
1295 GP_7_14_FN, FN_IP6_18_16,
1296 GP_7_13_FN, FN_IP6_15_14,
1297 GP_7_12_FN, FN_IP6_13_12,
1298 GP_7_11_FN, FN_IP6_11_10,
1299 GP_7_10_FN, FN_IP6_9_8,
1300 GP_7_9_FN, FN_IP16_11_10,
1301 GP_7_8_FN, FN_IP16_9_8,
1302 GP_7_7_FN, FN_IP16_7_6,
1303 GP_7_6_FN, FN_IP16_5_3,
1304 GP_7_5_FN, FN_IP16_2_0,
1305 GP_7_4_FN, FN_IP15_29_27,
1306 GP_7_3_FN, FN_IP15_26_24,
1307 GP_7_2_FN, FN_IP15_23_21,
1308 GP_7_1_FN, FN_IP15_20_18,
1309 GP_7_0_FN, FN_IP15_17_15 }
1310 },
1311
1312 /* IPSR0 - 5 */
1313
1314 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
1315 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
1316 /* IP6_31_30 [2] */
1317 0, 0, 0, 0,
1318 /* IP6_29_27 [3] */
1319 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
1320 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
1321 0, 0, 0,
1322 /* IP6_26_24 [3] */
1323 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
1324 FN_GPS_CLK_C, FN_GPS_CLK_D,
1325 0, 0, 0,
1326 /* IP6_23_21 [3] */
1327 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
1328 FN_SDA1_E, FN_MSIOF2_SYNC_E,
1329 0, 0, 0,
1330 /* IP6_20_19 [2] */
1331 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
1332 /* IP6_18_16 [3] */
1333 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
1334 0, 0, 0,
1335 /* IP6_15_14 [2] */
1336 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
1337 /* IP6_13_12 [2] */
1338 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
1339 /* IP6_11_10 [2] */
1340 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
1341 /* IP6_9_8 [2] */
1342 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
1343 /* IP6_7_6 [2] */
1344 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
1345 /* IP6_5_3 [3] */
1346 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
1347 FN_SCIFA2_RXD, FN_FMIN_E,
1348 0, 0,
1349 /* IP6_2_0 [3] */
1350 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
1351 FN_SCIF_CLK, 0, FN_BPFCLK_E,
1352 0, 0, }
1353 },
1354
1355 /* IPSR7 - 10 */
1356
1357 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
1358 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
1359 3, 3, 3, 3, 3) {
1360 /* IP11_31_30 [2] */
1361 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
1362 /* IP11_29_28 [2] */
1363 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
1364 /* IP11_27 [1] */
1365 FN_VI1_DATA7, FN_AVB_MDC,
1366 /* IP11_26 [1] */
1367 FN_VI1_DATA6, FN_AVB_MAGIC,
1368 /* IP11_25 [1] */
1369 FN_VI1_DATA5, FN_AVB_RX_DV,
1370 /* IP11_24 [1] */
1371 FN_VI1_DATA4, FN_AVB_MDIO,
1372 /* IP11_23 [1] */
1373 FN_VI1_DATA3, FN_AVB_RX_ER,
1374 /* IP11_22 [1] */
1375 FN_VI1_DATA2, FN_AVB_RXD7,
1376 /* IP11_21 [1] */
1377 FN_VI1_DATA1, FN_AVB_RXD6,
1378 /* IP11_20 [1] */
1379 FN_VI1_DATA0, FN_AVB_RXD5,
1380 /* IP11_19 [1] */
1381 FN_VI1_CLK, FN_AVB_RXD4,
1382 /* IP11_18_17 [2] */
1383 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
1384 /* IP11_16_15 [2] */
1385 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
1386 /* IP11_14_12 [3] */
1387 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
1388 FN_RX4_B, FN_SCIFA4_RXD_B,
1389 0, 0, 0,
1390 /* IP11_11_9 [3] */
1391 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
1392 FN_TX4_B, FN_SCIFA4_TXD_B,
1393 0, 0, 0,
1394 /* IP11_8_6 [3] */
1395 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
1396 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
1397 /* IP11_5_3 [3] */
1398 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
1399 0, 0, 0,
1400 /* IP11_2_0 [3] */
1401 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
1402 0, 0, 0, }
1403 },
1404 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
1405 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
1406 /* IP12_31_30 [2] */
1407 0, 0, 0, 0,
1408 /* IP12_29_27 [3] */
1409 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
1410 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
1411 0, 0, 0,
1412 /* IP12_26_24 [3] */
1413 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
1414 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
1415 0, 0, 0,
1416 /* IP12_23_22 [2] */
1417 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
1418 /* IP12_21_20 [2] */
1419 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
1420 /* IP12_19_18 [2] */
1421 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
1422 /* IP12_17_16 [2] */
1423 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
1424 /* IP12_15_13 [3] */
1425 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
1426 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
1427 0, 0, 0,
1428 /* IP12_12_10 [3] */
1429 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
1430 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
1431 0, 0, 0,
1432 /* IP12_9_7 [3] */
1433 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
1434 FN_SDA2_D, FN_MSIOF1_SCK_E,
1435 0, 0, 0,
1436 /* IP12_6_4 [3] */
1437 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
1438 FN_SCL2_D, FN_MSIOF1_RXD_E,
1439 0, 0, 0,
1440 /* IP12_3_2 [2] */
1441 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
1442 /* IP12_1_0 [2] */
1443 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
1444 },
1445 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
1446 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
1447 3, 2, 2, 3) {
1448 /* IP13_31 [1] */
1449 0, 0,
1450 /* IP13_30_28 [3] */
1451 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
1452 0, 0, 0, 0,
1453 /* IP13_27 [1] */
1454 FN_SD1_DATA3, FN_IERX_B,
1455 /* IP13_26 [1] */
1456 FN_SD1_DATA2, FN_IECLK_B,
1457 /* IP13_25 [1] */
1458 FN_SD1_DATA1, FN_IETX_B,
1459 /* IP13_24_23 [2] */
1460 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
1461 /* IP13_22 [1] */
1462 FN_SD1_CMD, FN_REMOCON_B,
1463 /* IP13_21_19 [3] */
1464 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
1465 FN_SCIFA5_RXD_B, FN_RX3_C,
1466 0, 0,
1467 /* IP13_18_16 [3] */
1468 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
1469 FN_SCIFA5_TXD_B, FN_TX3_C,
1470 0, 0,
1471 /* IP13_15 [1] */
1472 FN_SD0_DATA3, FN_SSL_B,
1473 /* IP13_14 [1] */
1474 FN_SD0_DATA2, FN_IO3_B,
1475 /* IP13_13 [1] */
1476 FN_SD0_DATA1, FN_IO2_B,
1477 /* IP13_12 [1] */
1478 FN_SD0_DATA0, FN_MISO_IO1_B,
1479 /* IP13_11 [1] */
1480 FN_SD0_CMD, FN_MOSI_IO0_B,
1481 /* IP13_10 [1] */
1482 FN_SD0_CLK, FN_SPCLK_B,
1483 /* IP13_9_7 [3] */
1484 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
1485 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
1486 0, 0, 0,
1487 /* IP13_6_5 [2] */
1488 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
1489 /* IP13_4_3 [2] */
1490 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
1491 /* IP13_2_0 [3] */
1492 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
1493 FN_ADICLK_B, FN_MSIOF0_SS1_C,
1494 0, 0, 0, }
1495 },
1496 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
1497 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
1498 /* IP14_31_29 [3] */
1499 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
1500 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
1501 /* IP14_28_26 [3] */
1502 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
1503 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
1504 /* IP14_25_23 [3] */
1505 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
1506 0, 0, 0,
1507 /* IP14_22_20 [3] */
1508 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
1509 0, 0, 0,
1510 /* IP14_19_17 [3] */
1511 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
1512 FN_VI1_CLKENB_C, FN_VI1_G1_B,
1513 0, 0,
1514 /* IP14_16_14 [3] */
1515 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
1516 FN_VI1_CLK_C, FN_VI1_G0_B,
1517 0, 0,
1518 /* IP14_13_11 [3] */
1519 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
1520 0, 0, 0,
1521 /* IP14_10_8 [3] */
1522 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
1523 0, 0, 0,
1524 /* IP14_7 [1] */
1525 FN_SD2_DATA3, FN_MMC_D3,
1526 /* IP14_6 [1] */
1527 FN_SD2_DATA2, FN_MMC_D2,
1528 /* IP14_5 [1] */
1529 FN_SD2_DATA1, FN_MMC_D1,
1530 /* IP14_4 [1] */
1531 FN_SD2_DATA0, FN_MMC_D0,
1532 /* IP14_3 [1] */
1533 FN_SD2_CMD, FN_MMC_CMD,
1534 /* IP14_2 [1] */
1535 FN_SD2_CLK, FN_MMC_CLK,
1536 /* IP14_1_0 [2] */
1537 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
1538 },
1539 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
1540 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
1541 /* IP15_31_30 [2] */
1542 0, 0, 0, 0,
1543 /* IP15_29_27 [3] */
1544 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
1545 FN_CAN0_TX_B, FN_VI1_DATA5_C,
1546 0, 0,
1547 /* IP15_26_24 [3] */
1548 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
1549 FN_CAN0_RX_B, FN_VI1_DATA4_C,
1550 0, 0,
1551 /* IP15_23_21 [3] */
1552 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
1553 FN_TCLK2, FN_VI1_DATA3_C, 0,
1554 /* IP15_20_18 [3] */
1555 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
1556 0, 0, 0,
1557 /* IP15_17_15 [3] */
1558 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
1559 FN_TCLK1, FN_VI1_DATA1_C,
1560 0, 0,
1561 /* IP15_14_12 [3] */
1562 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
1563 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
1564 0, 0,
1565 /* IP15_11_9 [3] */
1566 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
1567 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
1568 0, 0,
1569 /* IP15_8_6 [3] */
1570 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
1571 FN_PWM5_B, FN_SCIFA3_TXD_C,
1572 0, 0, 0,
1573 /* IP15_5_4 [2] */
1574 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
1575 /* IP15_3_2 [2] */
1576 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
1577 /* IP15_1_0 [2] */
1578 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
1579 },
1580 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
1581 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
1582 /* IP16_31_28 [4] */
1583 0, 0, 0, 0, 0, 0, 0, 0,
1584 0, 0, 0, 0, 0, 0, 0, 0,
1585 /* IP16_27_24 [4] */
1586 0, 0, 0, 0, 0, 0, 0, 0,
1587 0, 0, 0, 0, 0, 0, 0, 0,
1588 /* IP16_23_20 [4] */
1589 0, 0, 0, 0, 0, 0, 0, 0,
1590 0, 0, 0, 0, 0, 0, 0, 0,
1591 /* IP16_19_16 [4] */
1592 0, 0, 0, 0, 0, 0, 0, 0,
1593 0, 0, 0, 0, 0, 0, 0, 0,
1594 /* IP16_15_12 [4] */
1595 0, 0, 0, 0, 0, 0, 0, 0,
1596 0, 0, 0, 0, 0, 0, 0, 0,
1597 /* IP16_11_10 [2] */
1598 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
1599 /* IP16_9_8 [2] */
1600 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
1601 /* IP16_7_6 [2] */
1602 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
1603 /* IP16_5_3 [3] */
1604 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
1605 FN_GLO_SS_C, FN_VI1_DATA7_C,
1606 0, 0, 0,
1607 /* IP16_2_0 [3] */
1608 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
1609 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
1610 0, 0, 0, }
1611 },
1612 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1613 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
1614 3, 2, 2, 2, 1, 2, 2, 2) {
1615 /* RESEVED [1] */
1616 0, 0,
1617 /* SEL_SCIF1 [2] */
1618 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
1619 /* SEL_SCIFB [2] */
1620 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
1621 /* SEL_SCIFB2 [2] */
1622 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
1623 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
1624 /* SEL_SCIFB1 [3] */
1625 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
1626 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
1627 0, 0, 0, 0,
1628 /* SEL_SCIFA1 [2] */
1629 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
1630 /* SEL_SSI9 [1] */
1631 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
1632 /* SEL_SCFA [1] */
1633 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
1634 /* SEL_QSP [1] */
1635 FN_SEL_QSP_0, FN_SEL_QSP_1,
1636 /* SEL_SSI7 [1] */
1637 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
1638 /* SEL_HSCIF1 [3] */
1639 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
1640 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
1641 0, 0, 0,
1642 /* RESEVED [2] */
1643 0, 0, 0, 0,
1644 /* SEL_VI1 [2] */
1645 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
1646 /* RESEVED [2] */
1647 0, 0, 0, 0,
1648 /* SEL_TMU [1] */
1649 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
1650 /* SEL_LBS [2] */
1651 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
1652 /* SEL_TSIF0 [2] */
1653 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
1654 /* SEL_SOF0 [2] */
1655 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
1656 },
1657 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
1658 3, 1, 1, 3, 2, 1, 1, 2, 2,
1659 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
1660 /* SEL_SCIF0 [3] */
1661 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
1662 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
1663 0, 0, 0,
1664 /* RESEVED [1] */
1665 0, 0,
1666 /* SEL_SCIF [1] */
1667 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
1668 /* SEL_CAN0 [3] */
1669 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
1670 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
1671 0, 0,
1672 /* SEL_CAN1 [2] */
1673 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
1674 /* RESEVED [1] */
1675 0, 0,
1676 /* SEL_SCIFA2 [1] */
1677 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
1678 /* SEL_SCIF4 [2] */
1679 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
1680 /* RESEVED [2] */
1681 0, 0, 0, 0,
1682 /* SEL_ADG [1] */
1683 FN_SEL_ADG_0, FN_SEL_ADG_1,
1684 /* SEL_FM [3] */
1685 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
1686 FN_SEL_FM_3, FN_SEL_FM_4,
1687 0, 0, 0,
1688 /* SEL_SCIFA5 [2] */
1689 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
1690 /* RESEVED [1] */
1691 0, 0,
1692 /* SEL_GPS [2] */
1693 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
1694 /* SEL_SCIFA4 [2] */
1695 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
1696 /* SEL_SCIFA3 [2] */
1697 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
1698 /* SEL_SIM [1] */
1699 FN_SEL_SIM_0, FN_SEL_SIM_1,
1700 /* RESEVED [1] */
1701 0, 0,
1702 /* SEL_SSI8 [1] */
1703 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
1704 },
1705 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
1706 2, 2, 2, 2, 2, 2, 2, 2,
1707 1, 1, 2, 2, 3, 2, 2, 2, 1) {
1708 /* SEL_HSCIF2 [2] */
1709 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
1710 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
1711 /* SEL_CANCLK [2] */
1712 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
1713 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
1714 /* SEL_IIC8 [2] */
1715 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
1716 /* SEL_IIC7 [2] */
1717 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
1718 /* SEL_IIC4 [2] */
1719 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
1720 /* SEL_IIC3 [2] */
1721 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
1722 /* SEL_SCIF3 [2] */
1723 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
1724 /* SEL_IEB [2] */
1725 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
1726 /* SEL_MMC [1] */
1727 FN_SEL_MMC_0, FN_SEL_MMC_1,
1728 /* SEL_SCIF5 [1] */
1729 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
1730 /* RESEVED [2] */
1731 0, 0, 0, 0,
1732 /* SEL_IIC2 [2] */
1733 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
1734 /* SEL_IIC1 [3] */
1735 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
1736 FN_SEL_IIC1_4,
1737 0, 0, 0,
1738 /* SEL_IIC0 [2] */
1739 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
1740 /* RESEVED [2] */
1741 0, 0, 0, 0,
1742 /* RESEVED [2] */
1743 0, 0, 0, 0,
1744 /* RESEVED [1] */
1745 0, 0, }
1746 },
1747 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
1748 3, 2, 2, 1, 1, 1, 1, 3, 2,
1749 2, 3, 1, 1, 1, 2, 2, 2, 2) {
1750 /* SEL_SOF1 [3] */
1751 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
1752 FN_SEL_SOF1_4,
1753 0, 0, 0,
1754 /* SEL_HSCIF0 [2] */
1755 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
1756 /* SEL_DIS [2] */
1757 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
1758 /* RESEVED [1] */
1759 0, 0,
1760 /* SEL_RAD [1] */
1761 FN_SEL_RAD_0, FN_SEL_RAD_1,
1762 /* SEL_RCN [1] */
1763 FN_SEL_RCN_0, FN_SEL_RCN_1,
1764 /* SEL_RSP [1] */
1765 FN_SEL_RSP_0, FN_SEL_RSP_1,
1766 /* SEL_SCIF2 [3] */
1767 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
1768 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
1769 0, 0, 0,
1770 /* RESEVED [2] */
1771 0, 0, 0, 0,
1772 /* RESEVED [2] */
1773 0, 0, 0, 0,
1774 /* SEL_SOF2 [3] */
1775 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
1776 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
1777 0, 0, 0,
1778 /* RESEVED [1] */
1779 0, 0,
1780 /* SEL_SSI1 [1] */
1781 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
1782 /* SEL_SSI0 [1] */
1783 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
1784 /* SEL_SSP [2] */
1785 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
1786 /* RESEVED [2] */
1787 0, 0, 0, 0,
1788 /* RESEVED [2] */
1789 0, 0, 0, 0,
1790 /* RESEVED [2] */
1791 0, 0, 0, 0, }
1792 },
1793 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
1794 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
1795 0, 0,
1796 0, 0,
1797 0, 0,
1798 0, 0,
1799 0, 0,
1800 0, 0,
1801 GP_1_25_IN, GP_1_25_OUT,
1802 GP_1_24_IN, GP_1_24_OUT,
1803 GP_1_23_IN, GP_1_23_OUT,
1804 GP_1_22_IN, GP_1_22_OUT,
1805 GP_1_21_IN, GP_1_21_OUT,
1806 GP_1_20_IN, GP_1_20_OUT,
1807 GP_1_19_IN, GP_1_19_OUT,
1808 GP_1_18_IN, GP_1_18_OUT,
1809 GP_1_17_IN, GP_1_17_OUT,
1810 GP_1_16_IN, GP_1_16_OUT,
1811 GP_1_15_IN, GP_1_15_OUT,
1812 GP_1_14_IN, GP_1_14_OUT,
1813 GP_1_13_IN, GP_1_13_OUT,
1814 GP_1_12_IN, GP_1_12_OUT,
1815 GP_1_11_IN, GP_1_11_OUT,
1816 GP_1_10_IN, GP_1_10_OUT,
1817 GP_1_9_IN, GP_1_9_OUT,
1818 GP_1_8_IN, GP_1_8_OUT,
1819 GP_1_7_IN, GP_1_7_OUT,
1820 GP_1_6_IN, GP_1_6_OUT,
1821 GP_1_5_IN, GP_1_5_OUT,
1822 GP_1_4_IN, GP_1_4_OUT,
1823 GP_1_3_IN, GP_1_3_OUT,
1824 GP_1_2_IN, GP_1_2_OUT,
1825 GP_1_1_IN, GP_1_1_OUT,
1826 GP_1_0_IN, GP_1_0_OUT, }
1827 },
1828 { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
1829 { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
1830 { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
1831 { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
1832 { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
1833 { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
1834 0, 0,
1835 0, 0,
1836 0, 0,
1837 0, 0,
1838 0, 0,
1839 0, 0,
1840 GP_7_25_IN, GP_7_25_OUT,
1841 GP_7_24_IN, GP_7_24_OUT,
1842 GP_7_23_IN, GP_7_23_OUT,
1843 GP_7_22_IN, GP_7_22_OUT,
1844 GP_7_21_IN, GP_7_21_OUT,
1845 GP_7_20_IN, GP_7_20_OUT,
1846 GP_7_19_IN, GP_7_19_OUT,
1847 GP_7_18_IN, GP_7_18_OUT,
1848 GP_7_17_IN, GP_7_17_OUT,
1849 GP_7_16_IN, GP_7_16_OUT,
1850 GP_7_15_IN, GP_7_15_OUT,
1851 GP_7_14_IN, GP_7_14_OUT,
1852 GP_7_13_IN, GP_7_13_OUT,
1853 GP_7_12_IN, GP_7_12_OUT,
1854 GP_7_11_IN, GP_7_11_OUT,
1855 GP_7_10_IN, GP_7_10_OUT,
1856 GP_7_9_IN, GP_7_9_OUT,
1857 GP_7_8_IN, GP_7_8_OUT,
1858 GP_7_7_IN, GP_7_7_OUT,
1859 GP_7_6_IN, GP_7_6_OUT,
1860 GP_7_5_IN, GP_7_5_OUT,
1861 GP_7_4_IN, GP_7_4_OUT,
1862 GP_7_3_IN, GP_7_3_OUT,
1863 GP_7_2_IN, GP_7_2_OUT,
1864 GP_7_1_IN, GP_7_1_OUT,
1865 GP_7_0_IN, GP_7_0_OUT, }
1866 },
1867 { },
1868 };
1869
1870 static struct pinmux_data_reg pinmux_data_regs[] = {
1871 { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
1872 { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
1873 0, 0, 0, 0,
1874 0, 0, GP_1_25_DATA, GP_1_24_DATA,
1875 GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
1876 GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
1877 GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
1878 GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
1879 GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
1880 GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
1881 },
1882 { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
1883 { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
1884 { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
1885 { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
1886 { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
1887 { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
1888 0, 0, 0, 0,
1889 0, 0, GP_7_25_DATA, GP_7_24_DATA,
1890 GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
1891 GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
1892 GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
1893 GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
1894 GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
1895 GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
1896 },
1897 { },
1898 };
1899
1900 static struct pinmux_info r8a7793_pinmux_info = {
1901 .name = "r8a7793_pfc",
1902
1903 .unlock_reg = 0xe6060000, /* PMMR */
1904
1905 .reserved_id = PINMUX_RESERVED,
1906 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1907 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1908 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1909 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1910 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1911
1912 .first_gpio = GPIO_GP_0_0,
1913 .last_gpio = GPIO_FN_CAN1_RX_B,
1914
1915 .gpios = pinmux_gpios,
1916 .cfg_regs = pinmux_config_regs,
1917 .data_regs = pinmux_data_regs,
1918
1919 .gpio_data = pinmux_data,
1920 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1921 };
1922
r8a7793_pinmux_init(void)1923 void r8a7793_pinmux_init(void)
1924 {
1925 register_pinmux(&r8a7793_pinmux_info);
1926 }
1927