1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Renesas Electronics Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __PFC_R8A7790_H__ 10*4882a593Smuzhiyun #define __PFC_R8A7790_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <sh_pfc.h> 13*4882a593Smuzhiyun #include <asm/gpio.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CPU_32_PORT(fn, pfx, sfx) \ 16*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 17*4882a593Smuzhiyun PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ 18*4882a593Smuzhiyun PORT_1(fn, pfx##31, sfx) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CPU_32_PORT2(fn, pfx, sfx) \ 21*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 22*4882a593Smuzhiyun PORT_10(fn, pfx##2, sfx) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #if defined(CONFIG_R8A7790) 25*4882a593Smuzhiyun #define CPU_32_PORT1(fn, pfx, sfx) \ 26*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 27*4882a593Smuzhiyun PORT_10(fn, pfx##2, sfx) \ 28*4882a593Smuzhiyun /* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ 29*4882a593Smuzhiyun #define CPU_ALL_PORT(fn, pfx, sfx) \ 30*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_0_, sfx), \ 31*4882a593Smuzhiyun CPU_32_PORT1(fn, pfx##_1_, sfx), \ 32*4882a593Smuzhiyun CPU_32_PORT2(fn, pfx##_2_, sfx), \ 33*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_3_, sfx), \ 34*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_4_, sfx), \ 35*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_5_, sfx) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #elif defined(CONFIG_R8A7791) 38*4882a593Smuzhiyun #define CPU_32_PORT1(fn, pfx, sfx) \ 39*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 40*4882a593Smuzhiyun PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ 41*4882a593Smuzhiyun PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ 42*4882a593Smuzhiyun PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * GP_0_0_DATA -> GP_7_25_DATA 46*4882a593Smuzhiyun * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31] 47*4882a593Smuzhiyun * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31]) 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define CPU_ALL_PORT(fn, pfx, sfx) \ 50*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_0_, sfx), \ 51*4882a593Smuzhiyun CPU_32_PORT1(fn, pfx##_1_, sfx), \ 52*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_2_, sfx), \ 53*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_3_, sfx), \ 54*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_4_, sfx), \ 55*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_5_, sfx), \ 56*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_6_, sfx), \ 57*4882a593Smuzhiyun CPU_32_PORT1(fn, pfx##_7_, sfx) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #elif defined(CONFIG_R8A7792) 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * GP_0_0_DATA -> GP_11_29_DATA 62*4882a593Smuzhiyun * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31] 63*4882a593Smuzhiyun * GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31]) 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define CPU_32_PORT0_28(fn, pfx, sfx) \ 66*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 67*4882a593Smuzhiyun PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ 68*4882a593Smuzhiyun PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ 69*4882a593Smuzhiyun PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ 70*4882a593Smuzhiyun PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \ 71*4882a593Smuzhiyun PORT_1(fn, pfx##28, sfx) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define CPU_32_PORT0_22(fn, pfx, sfx) \ 74*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 75*4882a593Smuzhiyun PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ 76*4882a593Smuzhiyun PORT_1(fn, pfx##22, sfx) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define CPU_32_PORT0_27(fn, pfx, sfx) \ 79*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 80*4882a593Smuzhiyun PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ 81*4882a593Smuzhiyun PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ 82*4882a593Smuzhiyun PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ 83*4882a593Smuzhiyun PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define CPU_32_PORT0_16(fn, pfx, sfx) \ 86*4882a593Smuzhiyun PORT_10(fn, pfx, sfx), \ 87*4882a593Smuzhiyun PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \ 88*4882a593Smuzhiyun PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \ 89*4882a593Smuzhiyun PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \ 90*4882a593Smuzhiyun PORT_1(fn, pfx##16, sfx) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define CPU_ALL_PORT(fn, pfx, sfx) \ 93*4882a593Smuzhiyun CPU_32_PORT0_28(fn, pfx##_0_, sfx), \ 94*4882a593Smuzhiyun CPU_32_PORT0_22(fn, pfx##_1_, sfx), \ 95*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_2_, sfx), \ 96*4882a593Smuzhiyun CPU_32_PORT0_27(fn, pfx##_3_, sfx), \ 97*4882a593Smuzhiyun CPU_32_PORT0_16(fn, pfx##_4_, sfx), \ 98*4882a593Smuzhiyun CPU_32_PORT0_16(fn, pfx##_5_, sfx), \ 99*4882a593Smuzhiyun CPU_32_PORT0_16(fn, pfx##_6_, sfx), \ 100*4882a593Smuzhiyun CPU_32_PORT0_16(fn, pfx##_7_, sfx), \ 101*4882a593Smuzhiyun CPU_32_PORT0_16(fn, pfx##_8_, sfx), \ 102*4882a593Smuzhiyun CPU_32_PORT0_16(fn, pfx##_9_, sfx), \ 103*4882a593Smuzhiyun CPU_32_PORT(fn, pfx##_10_, sfx), \ 104*4882a593Smuzhiyun CPU_32_PORT2(fn, pfx##_11_, sfx) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #else 107*4882a593Smuzhiyun #error "NO support" 108*4882a593Smuzhiyun #endif 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) 111*4882a593Smuzhiyun #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ 112*4882a593Smuzhiyun GP##pfx##_IN, GP##pfx##_OUT) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT 115*4882a593Smuzhiyun #define _GP_INDT(pfx, sfx) GP##pfx##_DATA 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) 118*4882a593Smuzhiyun #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) 119*4882a593Smuzhiyun #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define PORT_10_REV(fn, pfx, sfx) \ 122*4882a593Smuzhiyun PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ 123*4882a593Smuzhiyun PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ 124*4882a593Smuzhiyun PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ 125*4882a593Smuzhiyun PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ 126*4882a593Smuzhiyun PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CPU_32_PORT_REV(fn, pfx, sfx) \ 129*4882a593Smuzhiyun PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ 130*4882a593Smuzhiyun PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ 131*4882a593Smuzhiyun PORT_10_REV(fn, pfx, sfx) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) 134*4882a593Smuzhiyun #define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) 137*4882a593Smuzhiyun #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ 138*4882a593Smuzhiyun FN_##ipsr, FN_##fn) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #endif /* __PFC_R8A7790_H__ */ 141