1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S 3*4882a593Smuzhiyun * This file is lowlevel initialize routine. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file is based on the arch/arm/cpu/armv8/start.S 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * (C) Copyright 2013 10*4882a593Smuzhiyun * David Feng <fenghua@phytium.com.cn> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun#include <asm-offsets.h> 16*4882a593Smuzhiyun#include <config.h> 17*4882a593Smuzhiyun#include <linux/linkage.h> 18*4882a593Smuzhiyun#include <asm/macro.h> 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunENTRY(lowlevel_init) 21*4882a593Smuzhiyun mov x29, lr /* Save LR */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun#ifndef CONFIG_ARMV8_MULTIENTRY 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * For single-entry systems the lowlevel init is very simple. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun ldr x0, =GICD_BASE 28*4882a593Smuzhiyun bl gic_init_secure 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun#else /* CONFIG_ARMV8_MULTIENTRY is set */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 33*4882a593Smuzhiyun branch_if_slave x0, 1f 34*4882a593Smuzhiyun ldr x0, =GICD_BASE 35*4882a593Smuzhiyun bl gic_init_secure 36*4882a593Smuzhiyun1: 37*4882a593Smuzhiyun#if defined(CONFIG_GICV3) 38*4882a593Smuzhiyun ldr x0, =GICR_BASE 39*4882a593Smuzhiyun bl gic_init_secure_percpu 40*4882a593Smuzhiyun#elif defined(CONFIG_GICV2) 41*4882a593Smuzhiyun ldr x0, =GICD_BASE 42*4882a593Smuzhiyun ldr x1, =GICC_BASE 43*4882a593Smuzhiyun bl gic_init_secure_percpu 44*4882a593Smuzhiyun#endif 45*4882a593Smuzhiyun#endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun branch_if_master x0, x1, 2f 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Slave should wait for master clearing spin table. 51*4882a593Smuzhiyun * This sync prevent salves observing incorrect 52*4882a593Smuzhiyun * value of spin table and jumping to wrong place. 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 55*4882a593Smuzhiyun#ifdef CONFIG_GICV2 56*4882a593Smuzhiyun ldr x0, =GICC_BASE 57*4882a593Smuzhiyun#endif 58*4882a593Smuzhiyun bl gic_wait_for_interrupt 59*4882a593Smuzhiyun#endif 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * All slaves will enter EL2 and optionally EL1. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun adr x4, lowlevel_in_el2 65*4882a593Smuzhiyun ldr x5, =ES_TO_AARCH64 66*4882a593Smuzhiyun bl armv8_switch_to_el2 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunlowlevel_in_el2: 69*4882a593Smuzhiyun#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 70*4882a593Smuzhiyun adr x4, lowlevel_in_el1 71*4882a593Smuzhiyun ldr x5, =ES_TO_AARCH64 72*4882a593Smuzhiyun bl armv8_switch_to_el1 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunlowlevel_in_el1: 75*4882a593Smuzhiyun#endif 76*4882a593Smuzhiyun#endif /* CONFIG_ARMV8_MULTIENTRY */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun bl s_init 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun2: 81*4882a593Smuzhiyun mov lr, x29 /* Restore LR */ 82*4882a593Smuzhiyun ret 83*4882a593SmuzhiyunENDPROC(lowlevel_init) 84