1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S 3*4882a593Smuzhiyun * This file is lager low level initialize. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013, 2014 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <config.h> 11*4882a593Smuzhiyun#include <linux/linkage.h> 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunENTRY(lowlevel_init) 14*4882a593Smuzhiyun mrc p15, 0, r4, c0, c0, 5 /* mpidr */ 15*4882a593Smuzhiyun orr r4, r4, r4, lsr #6 16*4882a593Smuzhiyun and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun b do_lowlevel_init 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun .pool 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun/* 23*4882a593Smuzhiyun * CPU ID #1-#3 come here 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun .align 4 26*4882a593Smuzhiyundo_cpu_waiting: 27*4882a593Smuzhiyun ldr r1, =0xe6180000 /* sysc */ 28*4882a593Smuzhiyun1: ldr r0, [r1, #0x20] /* sbar */ 29*4882a593Smuzhiyun tst r0, r0 30*4882a593Smuzhiyun beq 1b 31*4882a593Smuzhiyun bx r0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun/* 34*4882a593Smuzhiyun * Only CPU ID #0 comes here 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun .align 4 37*4882a593Smuzhiyundo_lowlevel_init: 38*4882a593Smuzhiyun ldr r2, =0xFF000044 /* PRR */ 39*4882a593Smuzhiyun ldr r1, [r2] 40*4882a593Smuzhiyun and r1, r1, #0x7F00 41*4882a593Smuzhiyun lsrs r1, r1, #8 42*4882a593Smuzhiyun cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ 43*4882a593Smuzhiyun beq _enable_actlr_smp 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* surpress wfe if ca15 */ 46*4882a593Smuzhiyun tst r4, #4 47*4882a593Smuzhiyun mrceq p15, 0, r0, c1, c0, 1 /* actlr */ 48*4882a593Smuzhiyun orreq r0, r0, #(1<<7) 49*4882a593Smuzhiyun mcreq p15, 0, r0, c1, c0, 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* and set l2 latency */ 52*4882a593Smuzhiyun mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */ 53*4882a593Smuzhiyun and r0, r0, #0xf00 54*4882a593Smuzhiyun lsr r0, r0, #8 55*4882a593Smuzhiyun tst r0, #1 /* only need for cluster 0 */ 56*4882a593Smuzhiyun bne _exit_init_l2_a15 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */ 59*4882a593Smuzhiyun and r1, r0, #7 60*4882a593Smuzhiyun cmp r1, #3 /* has already been set up */ 61*4882a593Smuzhiyun bicne r0, r0, #0xe7 62*4882a593Smuzhiyun orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ 63*4882a593Smuzhiyun#if defined(CONFIG_R8A7790) 64*4882a593Smuzhiyun orrne r0, r0, #0x20 /* L2CTLR[5] */ 65*4882a593Smuzhiyun#endif 66*4882a593Smuzhiyun mcrne p15, 1, r0, c9, c0, 2 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun b _exit_init_l2_a15 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun_enable_actlr_smp: /* R8A7794 only (CA7) */ 71*4882a593Smuzhiyun#ifndef CONFIG_DCACHE_OFF 72*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 1 73*4882a593Smuzhiyun orr r0, r0, #0x40 74*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 1 75*4882a593Smuzhiyun#endif 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun_exit_init_l2_a15: 78*4882a593Smuzhiyun ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) 79*4882a593Smuzhiyun sub sp, r3, #4 80*4882a593Smuzhiyun str lr, [sp] 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* initialize system */ 83*4882a593Smuzhiyun bl s_init 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun ldr lr, [sp] 86*4882a593Smuzhiyun mov pc, lr 87*4882a593Smuzhiyun nop 88*4882a593SmuzhiyunENDPROC(lowlevel_init) 89*4882a593Smuzhiyun .ltorg 90