1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_RCAR_GEN3_BASE_H 10*4882a593Smuzhiyun #define __ASM_ARCH_RCAR_GEN3_BASE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * R-Car (R8A7750) I/O Addresses 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define RWDT_BASE 0xE6020000 16*4882a593Smuzhiyun #define SWDT_BASE 0xE6030000 17*4882a593Smuzhiyun #define LBSC_BASE 0xEE220200 18*4882a593Smuzhiyun #define TMU_BASE 0xE61E0000 19*4882a593Smuzhiyun #define GPIO5_BASE 0xE6055000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* SCIF */ 22*4882a593Smuzhiyun #define SCIF0_BASE 0xE6E60000 23*4882a593Smuzhiyun #define SCIF1_BASE 0xE6E68000 24*4882a593Smuzhiyun #define SCIF2_BASE 0xE6E88000 25*4882a593Smuzhiyun #define SCIF3_BASE 0xE6C50000 26*4882a593Smuzhiyun #define SCIF4_BASE 0xE6C40000 27*4882a593Smuzhiyun #define SCIF5_BASE 0xE6F30000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Module stop status register */ 30*4882a593Smuzhiyun #define MSTPSR0 0xE6150030 31*4882a593Smuzhiyun #define MSTPSR1 0xE6150038 32*4882a593Smuzhiyun #define MSTPSR2 0xE6150040 33*4882a593Smuzhiyun #define MSTPSR3 0xE6150048 34*4882a593Smuzhiyun #define MSTPSR4 0xE615004C 35*4882a593Smuzhiyun #define MSTPSR5 0xE615003C 36*4882a593Smuzhiyun #define MSTPSR6 0xE61501C0 37*4882a593Smuzhiyun #define MSTPSR7 0xE61501C4 38*4882a593Smuzhiyun #define MSTPSR8 0xE61509A0 39*4882a593Smuzhiyun #define MSTPSR9 0xE61509A4 40*4882a593Smuzhiyun #define MSTPSR10 0xE61509A8 41*4882a593Smuzhiyun #define MSTPSR11 0xE61509AC 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Realtime module stop control register */ 44*4882a593Smuzhiyun #define RMSTPCR0 0xE6150110 45*4882a593Smuzhiyun #define RMSTPCR1 0xE6150114 46*4882a593Smuzhiyun #define RMSTPCR2 0xE6150118 47*4882a593Smuzhiyun #define RMSTPCR3 0xE615011C 48*4882a593Smuzhiyun #define RMSTPCR4 0xE6150120 49*4882a593Smuzhiyun #define RMSTPCR5 0xE6150124 50*4882a593Smuzhiyun #define RMSTPCR6 0xE6150128 51*4882a593Smuzhiyun #define RMSTPCR7 0xE615012C 52*4882a593Smuzhiyun #define RMSTPCR8 0xE6150980 53*4882a593Smuzhiyun #define RMSTPCR9 0xE6150984 54*4882a593Smuzhiyun #define RMSTPCR10 0xE6150988 55*4882a593Smuzhiyun #define RMSTPCR11 0xE615098C 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* System module stop control register */ 58*4882a593Smuzhiyun #define SMSTPCR0 0xE6150130 59*4882a593Smuzhiyun #define SMSTPCR1 0xE6150134 60*4882a593Smuzhiyun #define SMSTPCR2 0xE6150138 61*4882a593Smuzhiyun #define SMSTPCR3 0xE615013C 62*4882a593Smuzhiyun #define SMSTPCR4 0xE6150140 63*4882a593Smuzhiyun #define SMSTPCR5 0xE6150144 64*4882a593Smuzhiyun #define SMSTPCR6 0xE6150148 65*4882a593Smuzhiyun #define SMSTPCR7 0xE615014C 66*4882a593Smuzhiyun #define SMSTPCR8 0xE6150990 67*4882a593Smuzhiyun #define SMSTPCR9 0xE6150994 68*4882a593Smuzhiyun #define SMSTPCR10 0xE6150998 69*4882a593Smuzhiyun #define SMSTPCR11 0xE615099C 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* SDHI */ 72*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 73*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 74*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 75*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* PFC */ 78*4882a593Smuzhiyun #define PFC_PUEN5 0xE6060414 79*4882a593Smuzhiyun #define PUEN_SSI_SDATA4 BIT(17) 80*4882a593Smuzhiyun #define PFC_PUEN6 0xE6060418 81*4882a593Smuzhiyun #define PUEN_USB1_OVC (1 << 2) 82*4882a593Smuzhiyun #define PUEN_USB1_PWEN (1 << 1) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* IICDVFS (I2C) */ 85*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 88*4882a593Smuzhiyun #include <asm/types.h> 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* RWDT */ 91*4882a593Smuzhiyun struct rcar_rwdt { 92*4882a593Smuzhiyun u32 rwtcnt; 93*4882a593Smuzhiyun u32 rwtcsra; 94*4882a593Smuzhiyun u32 rwtcsrb; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* SWDT */ 98*4882a593Smuzhiyun struct rcar_swdt { 99*4882a593Smuzhiyun u32 swtcnt; 100*4882a593Smuzhiyun u32 swtcsra; 101*4882a593Smuzhiyun u32 swtcsrb; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun #endif 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */ 106