1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * arch/arm/mach-rmobile/include/mach/r8a7795.h 3*4882a593Smuzhiyun * This file defines registers and value for r8a7795. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_R8A7795_H 11*4882a593Smuzhiyun #define __ASM_ARCH_R8A7795_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "rcar-gen3-base.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Module stop control/status register bits */ 16*4882a593Smuzhiyun #define MSTP0_BITS 0x00640800 17*4882a593Smuzhiyun #define MSTP1_BITS 0xF3EE9390 18*4882a593Smuzhiyun #define MSTP2_BITS 0x340FAFDC 19*4882a593Smuzhiyun #define MSTP3_BITS 0xD80C7CDF 20*4882a593Smuzhiyun #define MSTP4_BITS 0x80000184 21*4882a593Smuzhiyun #define MSTP5_BITS 0x40BFFF46 22*4882a593Smuzhiyun #define MSTP6_BITS 0xE5FBEECF 23*4882a593Smuzhiyun #define MSTP7_BITS 0x39FFFF0E 24*4882a593Smuzhiyun #define MSTP8_BITS 0x01F19FF4 25*4882a593Smuzhiyun #define MSTP9_BITS 0xFFDFFFFF 26*4882a593Smuzhiyun #define MSTP10_BITS 0xFFFEFFE0 27*4882a593Smuzhiyun #define MSTP11_BITS 0x00000000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* SDHI */ 30*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 31*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 32*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ 33*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ 34*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __ASM_ARCH_R8A7795_H */ 37