1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * arch/arm/include/asm/arch-rmobile/r8a7793.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_R8A7793_H 10*4882a593Smuzhiyun #define __ASM_ARCH_R8A7793_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "rcar-base.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * R8A7793 I/O Addresses 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* SH-I2C */ 19*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* SDHI */ 22*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 23*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 24*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define DBSC3_1_QOS_R0_BASE 0xE67A1000 27*4882a593Smuzhiyun #define DBSC3_1_QOS_R1_BASE 0xE67A1100 28*4882a593Smuzhiyun #define DBSC3_1_QOS_R2_BASE 0xE67A1200 29*4882a593Smuzhiyun #define DBSC3_1_QOS_R3_BASE 0xE67A1300 30*4882a593Smuzhiyun #define DBSC3_1_QOS_R4_BASE 0xE67A1400 31*4882a593Smuzhiyun #define DBSC3_1_QOS_R5_BASE 0xE67A1500 32*4882a593Smuzhiyun #define DBSC3_1_QOS_R6_BASE 0xE67A1600 33*4882a593Smuzhiyun #define DBSC3_1_QOS_R7_BASE 0xE67A1700 34*4882a593Smuzhiyun #define DBSC3_1_QOS_R8_BASE 0xE67A1800 35*4882a593Smuzhiyun #define DBSC3_1_QOS_R9_BASE 0xE67A1900 36*4882a593Smuzhiyun #define DBSC3_1_QOS_R10_BASE 0xE67A1A00 37*4882a593Smuzhiyun #define DBSC3_1_QOS_R11_BASE 0xE67A1B00 38*4882a593Smuzhiyun #define DBSC3_1_QOS_R12_BASE 0xE67A1C00 39*4882a593Smuzhiyun #define DBSC3_1_QOS_R13_BASE 0xE67A1D00 40*4882a593Smuzhiyun #define DBSC3_1_QOS_R14_BASE 0xE67A1E00 41*4882a593Smuzhiyun #define DBSC3_1_QOS_R15_BASE 0xE67A1F00 42*4882a593Smuzhiyun #define DBSC3_1_QOS_W0_BASE 0xE67A2000 43*4882a593Smuzhiyun #define DBSC3_1_QOS_W1_BASE 0xE67A2100 44*4882a593Smuzhiyun #define DBSC3_1_QOS_W2_BASE 0xE67A2200 45*4882a593Smuzhiyun #define DBSC3_1_QOS_W3_BASE 0xE67A2300 46*4882a593Smuzhiyun #define DBSC3_1_QOS_W4_BASE 0xE67A2400 47*4882a593Smuzhiyun #define DBSC3_1_QOS_W5_BASE 0xE67A2500 48*4882a593Smuzhiyun #define DBSC3_1_QOS_W6_BASE 0xE67A2600 49*4882a593Smuzhiyun #define DBSC3_1_QOS_W7_BASE 0xE67A2700 50*4882a593Smuzhiyun #define DBSC3_1_QOS_W8_BASE 0xE67A2800 51*4882a593Smuzhiyun #define DBSC3_1_QOS_W9_BASE 0xE67A2900 52*4882a593Smuzhiyun #define DBSC3_1_QOS_W10_BASE 0xE67A2A00 53*4882a593Smuzhiyun #define DBSC3_1_QOS_W11_BASE 0xE67A2B00 54*4882a593Smuzhiyun #define DBSC3_1_QOS_W12_BASE 0xE67A2C00 55*4882a593Smuzhiyun #define DBSC3_1_QOS_W13_BASE 0xE67A2D00 56*4882a593Smuzhiyun #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 57*4882a593Smuzhiyun #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define DBSC3_1_DBADJ2 0xE67A00C8 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * R8A7793 I/O Product Information 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Module stop control/status register bits */ 66*4882a593Smuzhiyun #define MSTP0_BITS 0x00640801 67*4882a593Smuzhiyun #define MSTP1_BITS 0x9B6C9B5A 68*4882a593Smuzhiyun #define MSTP2_BITS 0x100D21FC 69*4882a593Smuzhiyun #define MSTP3_BITS 0xF08CD810 70*4882a593Smuzhiyun #define MSTP4_BITS 0x800001C4 71*4882a593Smuzhiyun #define MSTP5_BITS 0x44C00046 72*4882a593Smuzhiyun #define MSTP7_BITS 0x05BFE618 73*4882a593Smuzhiyun #define MSTP8_BITS 0x40C0FE85 74*4882a593Smuzhiyun #define MSTP9_BITS 0xFF979FFF 75*4882a593Smuzhiyun #define MSTP10_BITS 0xFFFEFFE0 76*4882a593Smuzhiyun #define MSTP11_BITS 0x000001C0 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define R8A7793_CUT_ES2X 2 79*4882a593Smuzhiyun #define IS_R8A7793_ES2() \ 80*4882a593Smuzhiyun (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif /* __ASM_ARCH_R8A7793_H */ 83