1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * arch/arm/include/asm/arch-rmobile/r8a7792.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_R8A7792_H 10*4882a593Smuzhiyun #define __ASM_ARCH_R8A7792_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "rcar-base.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* SH-I2C */ 15*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 16*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Module stop control/status register bits */ 19*4882a593Smuzhiyun #define MSTP0_BITS 0x00400801 20*4882a593Smuzhiyun #define MSTP1_BITS 0x9B6F987F 21*4882a593Smuzhiyun #define MSTP2_BITS 0x108CE100 22*4882a593Smuzhiyun #define MSTP3_BITS 0x20004010 23*4882a593Smuzhiyun #define MSTP4_BITS 0x80000184 24*4882a593Smuzhiyun #define MSTP5_BITS 0x44C00004 25*4882a593Smuzhiyun #define MSTP7_BITS 0x01BF0000 26*4882a593Smuzhiyun #define MSTP8_BITS 0x1FE01FB0 27*4882a593Smuzhiyun #define MSTP9_BITS 0xFE2BFFB2 28*4882a593Smuzhiyun #define MSTP10_BITS 0x00001820 29*4882a593Smuzhiyun #define MSTP11_BITS 0x00000008 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SDHI */ 32*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* __ASM_ARCH_R8A7792_H */ 35