1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * arch/arm/include/asm/arch-rmobile/r8a7790.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013,2014 Renesas Electronics Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_R8A7790_H 10*4882a593Smuzhiyun #define __ASM_ARCH_R8A7790_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "rcar-base.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* SH-I2C */ 15*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 16*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Module stop control/status register bits */ 19*4882a593Smuzhiyun #define MSTP0_BITS 0x00640801 20*4882a593Smuzhiyun #define MSTP1_BITS 0xDB6E9BDF 21*4882a593Smuzhiyun #define MSTP2_BITS 0x300DA1FC 22*4882a593Smuzhiyun #define MSTP3_BITS 0xF08CF831 23*4882a593Smuzhiyun #define MSTP4_BITS 0x80000184 24*4882a593Smuzhiyun #define MSTP5_BITS 0x44C00046 25*4882a593Smuzhiyun #define MSTP7_BITS 0x07F30718 26*4882a593Smuzhiyun #define MSTP8_BITS 0x01F0FF84 27*4882a593Smuzhiyun #define MSTP9_BITS 0xF5979FCF 28*4882a593Smuzhiyun #define MSTP10_BITS 0xFFFEFFE0 29*4882a593Smuzhiyun #define MSTP11_BITS 0x00000000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SDHI */ 32*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 33*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 34*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 35*4882a593Smuzhiyun #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define R8A7790_CUT_ES2X 2 38*4882a593Smuzhiyun #define IS_R8A7790_ES2() \ 39*4882a593Smuzhiyun (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __ASM_ARCH_R8A7790_H */ 42