1*4882a593Smuzhiyun #ifndef __ASM_MACH_IRQS_H 2*4882a593Smuzhiyun #define __ASM_MACH_IRQS_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define NR_IRQS 1024 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* GIC */ 7*4882a593Smuzhiyun #define gic_spi(nr) ((nr) + 32) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* INTCA */ 10*4882a593Smuzhiyun #define evt2irq(evt) (((evt) >> 5) - 16) 11*4882a593Smuzhiyun #define irq2evt(irq) (((irq) + 16) << 5) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* INTCS */ 14*4882a593Smuzhiyun #define INTCS_VECT_BASE 0x2200 15*4882a593Smuzhiyun #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) 16*4882a593Smuzhiyun #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #endif /* __ASM_MACH_IRQS_H */ 19