1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Based on original Kirkwood support which is 5*4882a593Smuzhiyun * (C) Copyright 2009 6*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 7*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <config.h> 14*4882a593Smuzhiyun #include <asm/arch/cpu.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * orion5x_sdram_bar - reads SDRAM Base Address Register 20*4882a593Smuzhiyun */ orion5x_sdram_bar(enum memory_bank bank)21*4882a593Smuzhiyunu32 orion5x_sdram_bar(enum memory_bank bank) 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun struct orion5x_ddr_addr_decode_registers *winregs = 24*4882a593Smuzhiyun (struct orion5x_ddr_addr_decode_registers *) 25*4882a593Smuzhiyun ORION5X_DRAM_BASE; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun u32 result = 0; 28*4882a593Smuzhiyun u32 enable = 0x01 & winregs[bank].size; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun if ((!enable) || (bank > BANK3)) 31*4882a593Smuzhiyun return 0; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun result = winregs[bank].base; 34*4882a593Smuzhiyun return result; 35*4882a593Smuzhiyun } dram_init(void)36*4882a593Smuzhiyunint dram_init (void) 37*4882a593Smuzhiyun { 38*4882a593Smuzhiyun /* dram_init must store complete ramsize in gd->ram_size */ 39*4882a593Smuzhiyun gd->ram_size = get_ram_size( 40*4882a593Smuzhiyun (long *) orion5x_sdram_bar(0), 41*4882a593Smuzhiyun CONFIG_MAX_RAM_BANK_SIZE); 42*4882a593Smuzhiyun return 0; 43*4882a593Smuzhiyun } 44*4882a593Smuzhiyun dram_init_banksize(void)45*4882a593Smuzhiyunint dram_init_banksize(void) 46*4882a593Smuzhiyun { 47*4882a593Smuzhiyun int i; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 50*4882a593Smuzhiyun gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); 51*4882a593Smuzhiyun gd->bd->bi_dram[i].size = get_ram_size( 52*4882a593Smuzhiyun (long *) (gd->bd->bi_dram[i].start), 53*4882a593Smuzhiyun CONFIG_MAX_RAM_BANK_SIZE); 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun return 0; 57*4882a593Smuzhiyun } 58