1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Voltage Controller implementation for OMAP
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5*4882a593Smuzhiyun * Nishanth Menon
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
8*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
9*4882a593Smuzhiyun * published by the Free Software Foundation.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
13*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14*4882a593Smuzhiyun * GNU General Public License for more details.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <asm/omap_common.h>
19*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
20*4882a593Smuzhiyun #include <asm/arch/clock.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Register defines and masks for VC IP Block */
23*4882a593Smuzhiyun /* PRM_VC_CFG_I2C_MODE */
24*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6)
25*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4)
26*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3)
27*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0
28*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* PRM_VC_CFG_I2C_CLK */
31*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24
32*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF
33*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16
34*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF
35*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
36*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
37*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
38*4882a593Smuzhiyun #define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* PRM_VC_VAL_BYPASS */
41*4882a593Smuzhiyun #define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24)
42*4882a593Smuzhiyun #define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
43*4882a593Smuzhiyun #define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
44*4882a593Smuzhiyun #define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
45*4882a593Smuzhiyun #define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
46*4882a593Smuzhiyun #define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
47*4882a593Smuzhiyun #define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /**
50*4882a593Smuzhiyun * omap_vc_init() - Initialization for Voltage controller
51*4882a593Smuzhiyun * @speed_khz: I2C buspeed in KHz
52*4882a593Smuzhiyun */
omap_vc_init(u16 speed_khz)53*4882a593Smuzhiyun static void omap_vc_init(u16 speed_khz)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun u32 val;
56*4882a593Smuzhiyun u32 sys_clk_khz, cycles_hi, cycles_low;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun sys_clk_khz = get_sys_clk_freq() / 1000;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (speed_khz > 400) {
61*4882a593Smuzhiyun puts("higher speed requested - throttle to 400Khz\n");
62*4882a593Smuzhiyun speed_khz = 400;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * Setup the dedicated I2C controller for Voltage Control
67*4882a593Smuzhiyun * I2C clk - high period 40% low period 60%
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun speed_khz /= 10;
70*4882a593Smuzhiyun cycles_hi = sys_clk_khz * 4 / speed_khz;
71*4882a593Smuzhiyun cycles_low = sys_clk_khz * 6 / speed_khz;
72*4882a593Smuzhiyun /* values to be set in register - less by 5 & 7 respectively */
73*4882a593Smuzhiyun cycles_hi -= 5;
74*4882a593Smuzhiyun cycles_low -= 7;
75*4882a593Smuzhiyun val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
76*4882a593Smuzhiyun (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
77*4882a593Smuzhiyun writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun * Master code if there are multiple masters on the I2C_SR bus.
81*4882a593Smuzhiyun */
82*4882a593Smuzhiyun val = 0x0 << PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
83*4882a593Smuzhiyun /* No HS mode for now */
84*4882a593Smuzhiyun val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
85*4882a593Smuzhiyun writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /**
89*4882a593Smuzhiyun * omap_vc_bypass_send_value() - Send a data using VC Bypass command
90*4882a593Smuzhiyun * @sa: 7 bit I2C slave address of the PMIC
91*4882a593Smuzhiyun * @reg_addr: I2C register address(8 bit) address in PMIC
92*4882a593Smuzhiyun * @reg_data: what 8 bit data to write
93*4882a593Smuzhiyun */
omap_vc_bypass_send_value(u8 sa,u8 reg_addr,u8 reg_data)94*4882a593Smuzhiyun int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * Unfortunately we need to loop here instead of a defined time
98*4882a593Smuzhiyun * use arbitary large value
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun u32 timeout = 0xFFFF;
101*4882a593Smuzhiyun u32 reg_val;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK;
104*4882a593Smuzhiyun reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
105*4882a593Smuzhiyun reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* program VC to send data */
108*4882a593Smuzhiyun reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
109*4882a593Smuzhiyun reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
110*4882a593Smuzhiyun reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
111*4882a593Smuzhiyun writel(reg_val, (*prcm)->prm_vc_val_bypass);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Signal VC to send data */
114*4882a593Smuzhiyun writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
115*4882a593Smuzhiyun (*prcm)->prm_vc_val_bypass);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Wait on VC to complete transmission */
118*4882a593Smuzhiyun do {
119*4882a593Smuzhiyun reg_val = readl((*prcm)->prm_vc_val_bypass) &
120*4882a593Smuzhiyun PRM_VC_VAL_BYPASS_VALID_BIT;
121*4882a593Smuzhiyun if (!reg_val)
122*4882a593Smuzhiyun break;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun sdelay(100);
125*4882a593Smuzhiyun } while (--timeout);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* Optional: cleanup PRM_IRQSTATUS_Ax */
128*4882a593Smuzhiyun /* In case we can do something about it in future.. */
129*4882a593Smuzhiyun if (!timeout)
130*4882a593Smuzhiyun return -1;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* All good.. */
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
sri2c_init(void)136*4882a593Smuzhiyun void sri2c_init(void)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun static int sri2c = 1;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun if (sri2c) {
141*4882a593Smuzhiyun omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
142*4882a593Smuzhiyun sri2c = 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun return;
145*4882a593Smuzhiyun }
146