1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * TI SATA platform driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2013
5*4882a593Smuzhiyun * Texas Instruments, <www.ti.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <ahci.h>
12*4882a593Smuzhiyun #include <scsi.h>
13*4882a593Smuzhiyun #include <asm/arch/clock.h>
14*4882a593Smuzhiyun #include <asm/arch/sata.h>
15*4882a593Smuzhiyun #include <sata.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include "pipe3-phy.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static struct pipe3_dpll_map dpll_map_sata[] = {
20*4882a593Smuzhiyun {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
21*4882a593Smuzhiyun {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
22*4882a593Smuzhiyun {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
23*4882a593Smuzhiyun {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
24*4882a593Smuzhiyun {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
25*4882a593Smuzhiyun {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
26*4882a593Smuzhiyun { }, /* Terminator */
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct omap_pipe3 sata_phy = {
30*4882a593Smuzhiyun .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
31*4882a593Smuzhiyun /* .power_reg is updated at runtime */
32*4882a593Smuzhiyun .dpll_map = dpll_map_sata,
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
init_sata(int dev)35*4882a593Smuzhiyun int init_sata(int dev)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun int ret;
38*4882a593Smuzhiyun u32 val;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Power up the PHY */
43*4882a593Smuzhiyun phy_pipe3_power_on(&sata_phy);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Enable SATA module, No Idle, No Standby */
46*4882a593Smuzhiyun val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
47*4882a593Smuzhiyun writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return ret;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
reset_sata(int dev)54*4882a593Smuzhiyun int reset_sata(int dev)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* On OMAP platforms SATA provides the SCSI subsystem */
scsi_init(void)60*4882a593Smuzhiyun void scsi_init(void)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun init_sata(0);
63*4882a593Smuzhiyun scsi_scan(1);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
scsi_bus_reset(struct udevice * dev)66*4882a593Smuzhiyun int scsi_bus_reset(struct udevice *dev)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun ahci_reset((void __iomem *)DWC_AHSATA_BASE);
69*4882a593Smuzhiyun ahci_init((void __iomem *)DWC_AHSATA_BASE);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73