1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * EMIF programming
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2010
5*4882a593Smuzhiyun * Texas Instruments, <www.ti.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> for OMAP4
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/emif.h>
14*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
15*4882a593Smuzhiyun #include <asm/utils.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
18*4882a593Smuzhiyun #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
19*4882a593Smuzhiyun static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
20*4882a593Smuzhiyun static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
24*4882a593Smuzhiyun /* Base AC Timing values specified by JESD209-2 for 532MHz operation */
25*4882a593Smuzhiyun static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
26*4882a593Smuzhiyun .max_freq = 532000000,
27*4882a593Smuzhiyun .RL = 8,
28*4882a593Smuzhiyun .tRPab = 21,
29*4882a593Smuzhiyun .tRCD = 18,
30*4882a593Smuzhiyun .tWR = 15,
31*4882a593Smuzhiyun .tRASmin = 42,
32*4882a593Smuzhiyun .tRRD = 10,
33*4882a593Smuzhiyun .tWTRx2 = 15,
34*4882a593Smuzhiyun .tXSR = 140,
35*4882a593Smuzhiyun .tXPx2 = 15,
36*4882a593Smuzhiyun .tRFCab = 130,
37*4882a593Smuzhiyun .tRTPx2 = 15,
38*4882a593Smuzhiyun .tCKE = 3,
39*4882a593Smuzhiyun .tCKESR = 15,
40*4882a593Smuzhiyun .tZQCS = 90,
41*4882a593Smuzhiyun .tZQCL = 360,
42*4882a593Smuzhiyun .tZQINIT = 1000,
43*4882a593Smuzhiyun .tDQSCKMAXx2 = 11,
44*4882a593Smuzhiyun .tRASmax = 70,
45*4882a593Smuzhiyun .tFAW = 50
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Min tCK values specified by JESD209-2
50*4882a593Smuzhiyun * Min tCK specifies the minimum duration of some AC timing parameters in terms
51*4882a593Smuzhiyun * of the number of cycles. If the calculated number of cycles based on the
52*4882a593Smuzhiyun * absolute time value is less than the min tCK value, min tCK value should
53*4882a593Smuzhiyun * be used instead. This typically happens at low frequencies.
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun static const struct lpddr2_min_tck min_tck_jedec = {
56*4882a593Smuzhiyun .tRL = 3,
57*4882a593Smuzhiyun .tRP_AB = 3,
58*4882a593Smuzhiyun .tRCD = 3,
59*4882a593Smuzhiyun .tWR = 3,
60*4882a593Smuzhiyun .tRAS_MIN = 3,
61*4882a593Smuzhiyun .tRRD = 2,
62*4882a593Smuzhiyun .tWTR = 2,
63*4882a593Smuzhiyun .tXP = 2,
64*4882a593Smuzhiyun .tRTP = 2,
65*4882a593Smuzhiyun .tCKE = 3,
66*4882a593Smuzhiyun .tCKESR = 3,
67*4882a593Smuzhiyun .tFAW = 8
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static const struct lpddr2_ac_timings const*
71*4882a593Smuzhiyun jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
72*4882a593Smuzhiyun &timings_jedec_532_mhz
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct lpddr2_device_timings jedec_default_timings = {
76*4882a593Smuzhiyun .ac_timings = jedec_ac_timings,
77*4882a593Smuzhiyun .min_tck = &min_tck_jedec
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
emif_get_device_timings(u32 emif_nr,const struct lpddr2_device_timings ** cs0_device_timings,const struct lpddr2_device_timings ** cs1_device_timings)80*4882a593Smuzhiyun void emif_get_device_timings(u32 emif_nr,
81*4882a593Smuzhiyun const struct lpddr2_device_timings **cs0_device_timings,
82*4882a593Smuzhiyun const struct lpddr2_device_timings **cs1_device_timings)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun /* Assume Identical devices on EMIF1 & EMIF2 */
85*4882a593Smuzhiyun *cs0_device_timings = &jedec_default_timings;
86*4882a593Smuzhiyun *cs1_device_timings = NULL;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
89