1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Adaptive Body Bias programming sequence for OMAP5 family 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2013 5*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <asm/omap_common.h> 14*4882a593Smuzhiyun #include <asm/io.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Setup LDOVBB for OMAP5. 18*4882a593Smuzhiyun * On OMAP5+ some ABB settings are fused. They are handled 19*4882a593Smuzhiyun * in the following way: 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * 1. corresponding EFUSE register contains ABB enable bit 22*4882a593Smuzhiyun * and VSET value 23*4882a593Smuzhiyun * 2. If ABB enable bit is set to 1, than ABB should be 24*4882a593Smuzhiyun * enabled, otherwise ABB should be disabled 25*4882a593Smuzhiyun * 3. If ABB is enabled, than VSET value should be copied 26*4882a593Smuzhiyun * to corresponding MUX control register 27*4882a593Smuzhiyun */ abb_setup_ldovbb(u32 fuse,u32 ldovbb)28*4882a593Smuzhiyuns8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) 29*4882a593Smuzhiyun { 30*4882a593Smuzhiyun u32 vset; 31*4882a593Smuzhiyun u32 fuse_enable_mask = OMAP5_PROD_ABB_FUSE_ENABLE_MASK; 32*4882a593Smuzhiyun u32 fuse_vset_mask = OMAP5_PROD_ABB_FUSE_VSET_MASK; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun if (!is_omap54xx()) { 35*4882a593Smuzhiyun /* DRA7 */ 36*4882a593Smuzhiyun fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK; 37*4882a593Smuzhiyun fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK; 38*4882a593Smuzhiyun } 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * ABB parameters must be properly fused 41*4882a593Smuzhiyun * otherwise ABB should be disabled 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun vset = readl(fuse); 44*4882a593Smuzhiyun if (!(vset & fuse_enable_mask)) 45*4882a593Smuzhiyun return -1; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* prepare VSET value for LDOVBB mux register */ 48*4882a593Smuzhiyun vset &= fuse_vset_mask; 49*4882a593Smuzhiyun vset >>= ffs(fuse_vset_mask) - 1; 50*4882a593Smuzhiyun vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; 51*4882a593Smuzhiyun vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* setup LDOVBB using fused value */ 54*4882a593Smuzhiyun clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun return 0; 57*4882a593Smuzhiyun } 58