1 /*
2 *
3 * Common functions for OMAP4 based boards
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14 #include <common.h>
15 #include <palmas.h>
16 #include <asm/armv7.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/sys_proto.h>
19 #include <linux/sizes.h>
20 #include <asm/emif.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/omap_common.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
27
28 static const struct gpio_bank gpio_bank_44xx[6] = {
29 { (void *)OMAP44XX_GPIO1_BASE },
30 { (void *)OMAP44XX_GPIO2_BASE },
31 { (void *)OMAP44XX_GPIO3_BASE },
32 { (void *)OMAP44XX_GPIO4_BASE },
33 { (void *)OMAP44XX_GPIO5_BASE },
34 { (void *)OMAP44XX_GPIO6_BASE },
35 };
36
37 const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
38
39 #ifdef CONFIG_SPL_BUILD
40 /*
41 * Some tuning of IOs for optimal power and performance
42 */
do_io_settings(void)43 void do_io_settings(void)
44 {
45 u32 lpddr2io;
46
47 u32 omap4_rev = omap_revision();
48
49 if (omap4_rev == OMAP4430_ES1_0)
50 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
51 else if (omap4_rev == OMAP4430_ES2_0)
52 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
53 else
54 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
55
56 /* EMIF1 */
57 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
58 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
59 /* No pull for GR10 as per hw team's recommendation */
60 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
61 (*ctrl)->control_lpddr2io1_2);
62 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
63
64 /* EMIF2 */
65 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
66 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
67 /* No pull for GR10 as per hw team's recommendation */
68 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
69 (*ctrl)->control_lpddr2io2_2);
70 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
71
72 /*
73 * Some of these settings (TRIM values) come from eFuse and are
74 * in turn programmed in the eFuse at manufacturing time after
75 * calibration of the device. Do the software over-ride only if
76 * the device is not correctly trimmed
77 */
78 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
79
80 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
81 (*ctrl)->control_ldosram_iva_voltage_ctrl);
82
83 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
84 (*ctrl)->control_ldosram_mpu_voltage_ctrl);
85
86 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
87 (*ctrl)->control_ldosram_core_voltage_ctrl);
88 }
89
90 /*
91 * Over-ride the register
92 * i. unconditionally for all 4430
93 * ii. only if un-trimmed for 4460
94 */
95 if (!readl((*ctrl)->control_efuse_1))
96 writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
97
98 if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
99 writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
100 }
101 #endif /* CONFIG_SPL_BUILD */
102
103 /* dummy fuction for omap4 */
config_data_eye_leveling_samples(u32 emif_base)104 void config_data_eye_leveling_samples(u32 emif_base)
105 {
106 }
107
init_omap_revision(void)108 void init_omap_revision(void)
109 {
110 /*
111 * For some of the ES2/ES1 boards ID_CODE is not reliable:
112 * Also, ES1 and ES2 have different ARM revisions
113 * So use ARM revision for identification
114 */
115 unsigned int arm_rev = cortex_rev();
116
117 switch (arm_rev) {
118 case MIDR_CORTEX_A9_R0P1:
119 *omap_si_rev = OMAP4430_ES1_0;
120 break;
121 case MIDR_CORTEX_A9_R1P2:
122 switch (readl(CONTROL_ID_CODE)) {
123 case OMAP4_CONTROL_ID_CODE_ES2_0:
124 *omap_si_rev = OMAP4430_ES2_0;
125 break;
126 case OMAP4_CONTROL_ID_CODE_ES2_1:
127 *omap_si_rev = OMAP4430_ES2_1;
128 break;
129 case OMAP4_CONTROL_ID_CODE_ES2_2:
130 *omap_si_rev = OMAP4430_ES2_2;
131 break;
132 default:
133 *omap_si_rev = OMAP4430_ES2_0;
134 break;
135 }
136 break;
137 case MIDR_CORTEX_A9_R1P3:
138 *omap_si_rev = OMAP4430_ES2_3;
139 break;
140 case MIDR_CORTEX_A9_R2P10:
141 switch (readl(CONTROL_ID_CODE)) {
142 case OMAP4470_CONTROL_ID_CODE_ES1_0:
143 *omap_si_rev = OMAP4470_ES1_0;
144 break;
145 case OMAP4460_CONTROL_ID_CODE_ES1_1:
146 *omap_si_rev = OMAP4460_ES1_1;
147 break;
148 case OMAP4460_CONTROL_ID_CODE_ES1_0:
149 default:
150 *omap_si_rev = OMAP4460_ES1_0;
151 break;
152 }
153 break;
154 default:
155 *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
156 break;
157 }
158 }
159
omap_die_id(unsigned int * die_id)160 void omap_die_id(unsigned int *die_id)
161 {
162 die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
163 die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
164 die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
165 die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
166 }
167
168 #ifndef CONFIG_SYS_L2CACHE_OFF
v7_outer_cache_enable(void)169 void v7_outer_cache_enable(void)
170 {
171 omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
172 }
173
v7_outer_cache_disable(void)174 void v7_outer_cache_disable(void)
175 {
176 omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
177 }
178 #endif /* !CONFIG_SYS_L2CACHE_OFF */
179
vmmc_pbias_config(uint voltage)180 void vmmc_pbias_config(uint voltage)
181 {
182 u32 value = 0;
183
184 value = readl((*ctrl)->control_pbiaslite);
185 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
186 writel(value, (*ctrl)->control_pbiaslite);
187 value = readl((*ctrl)->control_pbiaslite);
188 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
189 writel(value, (*ctrl)->control_pbiaslite);
190 }
191