1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * EMIF programming
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2010
5*4882a593Smuzhiyun * Texas Instruments, <www.ti.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/emif.h>
14*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
15*4882a593Smuzhiyun #include <asm/utils.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
18*4882a593Smuzhiyun u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
19*4882a593Smuzhiyun u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
23*4882a593Smuzhiyun /* Base AC Timing values specified by JESD209-2 for 400MHz operation */
24*4882a593Smuzhiyun static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
25*4882a593Smuzhiyun .max_freq = 400000000,
26*4882a593Smuzhiyun .RL = 6,
27*4882a593Smuzhiyun .tRPab = 21,
28*4882a593Smuzhiyun .tRCD = 18,
29*4882a593Smuzhiyun .tWR = 15,
30*4882a593Smuzhiyun .tRASmin = 42,
31*4882a593Smuzhiyun .tRRD = 10,
32*4882a593Smuzhiyun .tWTRx2 = 15,
33*4882a593Smuzhiyun .tXSR = 140,
34*4882a593Smuzhiyun .tXPx2 = 15,
35*4882a593Smuzhiyun .tRFCab = 130,
36*4882a593Smuzhiyun .tRTPx2 = 15,
37*4882a593Smuzhiyun .tCKE = 3,
38*4882a593Smuzhiyun .tCKESR = 15,
39*4882a593Smuzhiyun .tZQCS = 90,
40*4882a593Smuzhiyun .tZQCL = 360,
41*4882a593Smuzhiyun .tZQINIT = 1000,
42*4882a593Smuzhiyun .tDQSCKMAXx2 = 11,
43*4882a593Smuzhiyun .tRASmax = 70,
44*4882a593Smuzhiyun .tFAW = 50
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
48*4882a593Smuzhiyun static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
49*4882a593Smuzhiyun .max_freq = 200000000,
50*4882a593Smuzhiyun .RL = 3,
51*4882a593Smuzhiyun .tRPab = 21,
52*4882a593Smuzhiyun .tRCD = 18,
53*4882a593Smuzhiyun .tWR = 15,
54*4882a593Smuzhiyun .tRASmin = 42,
55*4882a593Smuzhiyun .tRRD = 10,
56*4882a593Smuzhiyun .tWTRx2 = 20,
57*4882a593Smuzhiyun .tXSR = 140,
58*4882a593Smuzhiyun .tXPx2 = 15,
59*4882a593Smuzhiyun .tRFCab = 130,
60*4882a593Smuzhiyun .tRTPx2 = 15,
61*4882a593Smuzhiyun .tCKE = 3,
62*4882a593Smuzhiyun .tCKESR = 15,
63*4882a593Smuzhiyun .tZQCS = 90,
64*4882a593Smuzhiyun .tZQCL = 360,
65*4882a593Smuzhiyun .tZQINIT = 1000,
66*4882a593Smuzhiyun .tDQSCKMAXx2 = 11,
67*4882a593Smuzhiyun .tRASmax = 70,
68*4882a593Smuzhiyun .tFAW = 50
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * Min tCK values specified by JESD209-2
73*4882a593Smuzhiyun * Min tCK specifies the minimum duration of some AC timing parameters in terms
74*4882a593Smuzhiyun * of the number of cycles. If the calculated number of cycles based on the
75*4882a593Smuzhiyun * absolute time value is less than the min tCK value, min tCK value should
76*4882a593Smuzhiyun * be used instead. This typically happens at low frequencies.
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun static const struct lpddr2_min_tck min_tck_jedec = {
79*4882a593Smuzhiyun .tRL = 3,
80*4882a593Smuzhiyun .tRP_AB = 3,
81*4882a593Smuzhiyun .tRCD = 3,
82*4882a593Smuzhiyun .tWR = 3,
83*4882a593Smuzhiyun .tRAS_MIN = 3,
84*4882a593Smuzhiyun .tRRD = 2,
85*4882a593Smuzhiyun .tWTR = 2,
86*4882a593Smuzhiyun .tXP = 2,
87*4882a593Smuzhiyun .tRTP = 2,
88*4882a593Smuzhiyun .tCKE = 3,
89*4882a593Smuzhiyun .tCKESR = 3,
90*4882a593Smuzhiyun .tFAW = 8
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static const struct lpddr2_ac_timings const*
94*4882a593Smuzhiyun jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
95*4882a593Smuzhiyun &timings_jedec_200_mhz,
96*4882a593Smuzhiyun &timings_jedec_400_mhz
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun const struct lpddr2_device_timings jedec_default_timings = {
100*4882a593Smuzhiyun .ac_timings = jedec_ac_timings,
101*4882a593Smuzhiyun .min_tck = &min_tck_jedec
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
emif_get_device_timings(u32 emif_nr,const struct lpddr2_device_timings ** cs0_device_timings,const struct lpddr2_device_timings ** cs1_device_timings)104*4882a593Smuzhiyun void emif_get_device_timings(u32 emif_nr,
105*4882a593Smuzhiyun const struct lpddr2_device_timings **cs0_device_timings,
106*4882a593Smuzhiyun const struct lpddr2_device_timings **cs1_device_timings)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun /* Assume Identical devices on EMIF1 & EMIF2 */
109*4882a593Smuzhiyun *cs0_device_timings = &jedec_default_timings;
110*4882a593Smuzhiyun *cs1_device_timings = &jedec_default_timings;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
113