1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author : 6*4882a593Smuzhiyun * Tom Rini <trini@ti.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Initial Code from: 9*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 10*4882a593Smuzhiyun * Jian Zhang <jzhang@ti.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <common.h> 16*4882a593Smuzhiyun #include <jffs2/load_kernel.h> 17*4882a593Smuzhiyun #include <linux/mtd/rawnand.h> 18*4882a593Smuzhiyun #include <linux/mtd/omap_gpmc.h> 19*4882a593Smuzhiyun #include <asm/io.h> 20*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 21*4882a593Smuzhiyun #include <asm/arch/mem.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Many boards will want to know the results of the NAND_CMD_READID command 25*4882a593Smuzhiyun * in order to decide what to do about DDR initialization. This function 26*4882a593Smuzhiyun * allows us to do that very early and to pass those results back to the 27*4882a593Smuzhiyun * board so it can make whatever decisions need to be made. 28*4882a593Smuzhiyun */ identify_nand_chip(int * mfr,int * id)29*4882a593Smuzhiyunint identify_nand_chip(int *mfr, int *id) 30*4882a593Smuzhiyun { 31*4882a593Smuzhiyun int loops = 1000; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Make sure that we have setup GPMC for NAND correctly. */ 34*4882a593Smuzhiyun set_gpmc_cs0(MTD_DEV_TYPE_NAND); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun sdelay(2000); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Issue a RESET and then READID */ 39*4882a593Smuzhiyun writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); 40*4882a593Smuzhiyun writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); 41*4882a593Smuzhiyun while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) 42*4882a593Smuzhiyun != NAND_STATUS_READY) { 43*4882a593Smuzhiyun sdelay(100); 44*4882a593Smuzhiyun if (--loops == 0) 45*4882a593Smuzhiyun return 1; 46*4882a593Smuzhiyun } 47*4882a593Smuzhiyun writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Set the address to read to 0x0 */ 50*4882a593Smuzhiyun writeb(0x0, &gpmc_cfg->cs[0].nand_adr); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Read off the manufacturer and device id. */ 53*4882a593Smuzhiyun *mfr = readb(&gpmc_cfg->cs[0].nand_dat); 54*4882a593Smuzhiyun *id = readb(&gpmc_cfg->cs[0].nand_dat); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun return 0; 57*4882a593Smuzhiyun } 58