1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Author :
3*4882a593Smuzhiyun * Vaibhav Hiremath <hvaibhav@ti.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on mem.c and sdrc.c
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2010
8*4882a593Smuzhiyun * Texas Instruments Incorporated - http://www.ti.com/
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <asm/arch/mem.h>
16*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
17*4882a593Smuzhiyun #include <asm/arch/emif4.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun extern omap3_sysinfo sysinfo;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun * is_mem_sdr -
26*4882a593Smuzhiyun * - Return 1 if mem type in use is SDR
27*4882a593Smuzhiyun */
is_mem_sdr(void)28*4882a593Smuzhiyun u32 is_mem_sdr(void)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * get_sdr_cs_size -
35*4882a593Smuzhiyun * - Get size of chip select 0/1
36*4882a593Smuzhiyun */
get_sdr_cs_size(u32 cs)37*4882a593Smuzhiyun u32 get_sdr_cs_size(u32 cs)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun u32 size = 0;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* TODO: Calculate the size based on EMIF4 configuration */
42*4882a593Smuzhiyun if (cs == CS0)
43*4882a593Smuzhiyun size = CONFIG_SYS_CS0_SIZE;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return size;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * get_sdr_cs_offset -
50*4882a593Smuzhiyun * - Get offset of cs from cs0 start
51*4882a593Smuzhiyun */
get_sdr_cs_offset(u32 cs)52*4882a593Smuzhiyun u32 get_sdr_cs_offset(u32 cs)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u32 offset = 0;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return offset;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * do_emif4_init -
61*4882a593Smuzhiyun * - Init the emif4 module for DDR access
62*4882a593Smuzhiyun * - Early init routines, called from flash or SRAM.
63*4882a593Smuzhiyun */
do_emif4_init(void)64*4882a593Smuzhiyun static void do_emif4_init(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun unsigned int regval;
67*4882a593Smuzhiyun /* Set the DDR PHY parameters in PHY ctrl registers */
68*4882a593Smuzhiyun regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
69*4882a593Smuzhiyun EMIF4_DDR1_EXT_STRB_DIS);
70*4882a593Smuzhiyun writel(regval, &emif4_base->ddr_phyctrl1);
71*4882a593Smuzhiyun writel(regval, &emif4_base->ddr_phyctrl1_shdw);
72*4882a593Smuzhiyun writel(0, &emif4_base->ddr_phyctrl2);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Reset the DDR PHY and wait till completed */
75*4882a593Smuzhiyun regval = readl(&emif4_base->sdram_iodft_tlgc);
76*4882a593Smuzhiyun regval |= (1<<10);
77*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_iodft_tlgc);
78*4882a593Smuzhiyun /*Wait till that bit clears*/
79*4882a593Smuzhiyun while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0);
80*4882a593Smuzhiyun /*Re-verify the DDR PHY status*/
81*4882a593Smuzhiyun while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun regval |= (1<<0);
84*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_iodft_tlgc);
85*4882a593Smuzhiyun /* Set SDR timing registers */
86*4882a593Smuzhiyun regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
87*4882a593Smuzhiyun EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
88*4882a593Smuzhiyun EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
89*4882a593Smuzhiyun EMIF4_TIM1_T_RP);
90*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_time1);
91*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_time1_shdw);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
94*4882a593Smuzhiyun EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
95*4882a593Smuzhiyun EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
96*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_time2);
97*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_time2_shdw);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
100*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_time3);
101*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_time3_shdw);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Set the PWR control register */
104*4882a593Smuzhiyun regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
105*4882a593Smuzhiyun EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
106*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_pwr_mgmt);
107*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Set the DDR refresh rate control register */
110*4882a593Smuzhiyun regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
111*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_refresh_ctrl);
112*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* set the SDRAM configuration register */
115*4882a593Smuzhiyun regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
116*4882a593Smuzhiyun EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
117*4882a593Smuzhiyun EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
118*4882a593Smuzhiyun EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
119*4882a593Smuzhiyun EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
120*4882a593Smuzhiyun EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
121*4882a593Smuzhiyun writel(regval, &emif4_base->sdram_config);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun * dram_init -
126*4882a593Smuzhiyun * - Sets uboots idea of sdram size
127*4882a593Smuzhiyun */
dram_init(void)128*4882a593Smuzhiyun int dram_init(void)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun unsigned int size0 = 0, size1 = 0;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun size0 = get_sdr_cs_size(CS0);
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * If a second bank of DDR is attached to CS1 this is
135*4882a593Smuzhiyun * where it can be started. Early init code will init
136*4882a593Smuzhiyun * memory on CS0.
137*4882a593Smuzhiyun */
138*4882a593Smuzhiyun if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
139*4882a593Smuzhiyun size1 = get_sdr_cs_size(CS1);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun gd->ram_size = size0 + size1;
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
dram_init_banksize(void)145*4882a593Smuzhiyun int dram_init_banksize(void)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun unsigned int size0 = 0, size1 = 0;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun size0 = get_sdr_cs_size(CS0);
150*4882a593Smuzhiyun size1 = get_sdr_cs_size(CS1);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
153*4882a593Smuzhiyun gd->bd->bi_dram[0].size = size0;
154*4882a593Smuzhiyun gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
155*4882a593Smuzhiyun gd->bd->bi_dram[1].size = size1;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /*
161*4882a593Smuzhiyun * mem_init() -
162*4882a593Smuzhiyun * - Initialize memory subsystem
163*4882a593Smuzhiyun */
mem_init(void)164*4882a593Smuzhiyun void mem_init(void)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun do_emif4_init();
167*4882a593Smuzhiyun }
168