1 /*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 *
5 * Author :
6 * Manikandan Pillai <mani.pillai@ti.com>
7 *
8 * Derived from Beagle Board and OMAP3 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15 #include <common.h>
16 #include <asm/io.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clocks_omap3.h>
19 #include <asm/arch/mem.h>
20 #include <asm/arch/sys_proto.h>
21 #include <environment.h>
22 #include <command.h>
23
24 /******************************************************************************
25 * get_sys_clk_speed() - determine reference oscillator speed
26 * based on known 32kHz clock and gptimer.
27 *****************************************************************************/
get_osc_clk_speed(void)28 u32 get_osc_clk_speed(void)
29 {
30 u32 start, cstart, cend, cdiff, cdiv, val;
31 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
32 struct prm *prm_base = (struct prm *)PRM_BASE;
33 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
34 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
35
36 val = readl(&prm_base->clksrc_ctrl);
37
38 if (val & SYSCLKDIV_2)
39 cdiv = 2;
40 else
41 cdiv = 1;
42
43 /* enable timer2 */
44 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
45
46 /* select sys_clk for GPT1 */
47 writel(val, &prcm_base->clksel_wkup);
48
49 /* Enable I and F Clocks for GPT1 */
50 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
51 writel(val, &prcm_base->iclken_wkup);
52
53 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
54 writel(val, &prcm_base->fclken_wkup);
55
56 writel(0, &gpt1_base->tldr); /* start counting at 0 */
57 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
58
59 /* enable 32kHz source, determine sys_clk via gauging */
60
61 /* start time in 20 cycles */
62 start = 20 + readl(&s32k_base->s32k_cr);
63
64 /* dead loop till start time */
65 while (readl(&s32k_base->s32k_cr) < start);
66
67 /* get start sys_clk count */
68 cstart = readl(&gpt1_base->tcrr);
69
70 /* wait for 40 cycles */
71 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
72 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
73 cdiff = cend - cstart; /* get elapsed ticks */
74 cdiff *= cdiv;
75
76 /* based on number of ticks assign speed */
77 if (cdiff > 19000)
78 return S38_4M;
79 else if (cdiff > 15200)
80 return S26M;
81 else if (cdiff > 13000)
82 return S24M;
83 else if (cdiff > 9000)
84 return S19_2M;
85 else if (cdiff > 7600)
86 return S13M;
87 else
88 return S12M;
89 }
90
91 /******************************************************************************
92 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
93 * input oscillator clock frequency.
94 *****************************************************************************/
get_sys_clkin_sel(u32 osc_clk,u32 * sys_clkin_sel)95 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
96 {
97 switch(osc_clk) {
98 case S38_4M:
99 *sys_clkin_sel = 4;
100 break;
101 case S26M:
102 *sys_clkin_sel = 3;
103 break;
104 case S19_2M:
105 *sys_clkin_sel = 2;
106 break;
107 case S13M:
108 *sys_clkin_sel = 1;
109 break;
110 case S12M:
111 default:
112 *sys_clkin_sel = 0;
113 }
114 }
115
116 /*
117 * OMAP34XX/35XX specific functions
118 */
119
dpll3_init_34xx(u32 sil_index,u32 clk_index)120 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
121 {
122 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
123 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
124 void (*f_lock_pll) (u32, u32, u32, u32);
125 int xip_safe, p0, p1, p2, p3;
126
127 xip_safe = is_running_in_sram();
128
129 /* Moving to the right sysclk and ES rev base */
130 ptr = ptr + (3 * clk_index) + sil_index;
131
132 if (xip_safe) {
133 /*
134 * CORE DPLL
135 */
136 clrsetbits_le32(&prcm_base->clken_pll,
137 0x00000007, PLL_FAST_RELOCK_BYPASS);
138 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
139 LDELAY);
140
141 /*
142 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
143 * work. write another value and then default value.
144 */
145
146 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
147 clrsetbits_le32(&prcm_base->clksel1_emu,
148 0x001F0000, (CORE_M3X2 + 1) << 16) ;
149 clrsetbits_le32(&prcm_base->clksel1_emu,
150 0x001F0000, CORE_M3X2 << 16);
151
152 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
153 clrsetbits_le32(&prcm_base->clksel1_pll,
154 0xF8000000, ptr->m2 << 27);
155
156 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
157 clrsetbits_le32(&prcm_base->clksel1_pll,
158 0x07FF0000, ptr->m << 16);
159
160 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
161 clrsetbits_le32(&prcm_base->clksel1_pll,
162 0x00007F00, ptr->n << 8);
163
164 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
165 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
166
167 /* SSI */
168 clrsetbits_le32(&prcm_base->clksel_core,
169 0x00000F00, CORE_SSI_DIV << 8);
170 /* FSUSB */
171 clrsetbits_le32(&prcm_base->clksel_core,
172 0x00000030, CORE_FUSB_DIV << 4);
173 /* L4 */
174 clrsetbits_le32(&prcm_base->clksel_core,
175 0x0000000C, CORE_L4_DIV << 2);
176 /* L3 */
177 clrsetbits_le32(&prcm_base->clksel_core,
178 0x00000003, CORE_L3_DIV);
179 /* GFX */
180 clrsetbits_le32(&prcm_base->clksel_gfx,
181 0x00000007, GFX_DIV);
182 /* RESET MGR */
183 clrsetbits_le32(&prcm_base->clksel_wkup,
184 0x00000006, WKUP_RSM << 1);
185 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
186 clrsetbits_le32(&prcm_base->clken_pll,
187 0x000000F0, ptr->fsel << 4);
188 /* LOCK MODE */
189 clrsetbits_le32(&prcm_base->clken_pll,
190 0x00000007, PLL_LOCK);
191
192 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
193 LDELAY);
194 } else if (is_running_in_flash()) {
195 /*
196 * if running from flash, jump to small relocated code
197 * area in SRAM.
198 */
199 f_lock_pll = (void *) (SRAM_CLK_CODE);
200
201 p0 = readl(&prcm_base->clken_pll);
202 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
203 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
204 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
205
206 p1 = readl(&prcm_base->clksel1_pll);
207 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
208 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
209 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
210 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
211 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
212 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
213 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
214 clrbits_le32(&p1, 0x00000040);
215
216 p2 = readl(&prcm_base->clksel_core);
217 /* SSI */
218 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
219 /* FSUSB */
220 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
221 /* L4 */
222 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
223 /* L3 */
224 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
225
226 p3 = (u32)&prcm_base->idlest_ckgen;
227
228 (*f_lock_pll) (p0, p1, p2, p3);
229 }
230 }
231
dpll4_init_34xx(u32 sil_index,u32 clk_index)232 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
233 {
234 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
235 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
236
237 /* Moving it to the right sysclk base */
238 ptr = ptr + clk_index;
239
240 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
241 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
242 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
243
244 /*
245 * Errata 1.50 Workaround for OMAP3 ES1.0 only
246 * If using default divisors, write default divisor + 1
247 * and then the actual divisor value
248 */
249 /* M6 */
250 clrsetbits_le32(&prcm_base->clksel1_emu,
251 0x1F000000, (PER_M6X2 + 1) << 24);
252 clrsetbits_le32(&prcm_base->clksel1_emu,
253 0x1F000000, PER_M6X2 << 24);
254 /* M5 */
255 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
256 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
257 /* M4 */
258 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
259 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
260 /* M3 */
261 clrsetbits_le32(&prcm_base->clksel_dss,
262 0x00001F00, (PER_M3X2 + 1) << 8);
263 clrsetbits_le32(&prcm_base->clksel_dss,
264 0x00001F00, PER_M3X2 << 8);
265 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
267 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
268 /* Workaround end */
269
270 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
271 clrsetbits_le32(&prcm_base->clksel2_pll,
272 0x0007FF00, ptr->m << 8);
273
274 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
275 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
276
277 /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
278 clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
279
280 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
281 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
282 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
283 }
284
dpll5_init_34xx(u32 sil_index,u32 clk_index)285 static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
286 {
287 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
288 dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
289
290 /* Moving it to the right sysclk base */
291 ptr = ptr + clk_index;
292
293 /* PER2 DPLL (DPLL5) */
294 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
295 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
296 /* set M2 (usbtll_fck) */
297 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
298 /* set m (11-bit multiplier) */
299 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
300 /* set n (7-bit divider)*/
301 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
302 /* FREQSEL */
303 clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
304 /* lock mode */
305 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
306 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
307 }
308
mpu_init_34xx(u32 sil_index,u32 clk_index)309 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
310 {
311 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
312 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
313
314 /* Moving to the right sysclk and ES rev base */
315 ptr = ptr + (3 * clk_index) + sil_index;
316
317 /* MPU DPLL (unlocked already) */
318
319 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
320 clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
321 0x0000001F, ptr->m2);
322
323 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
324 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
325 0x0007FF00, ptr->m << 8);
326
327 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
328 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
329 0x0000007F, ptr->n);
330
331 /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
332 clrsetbits_le32(&prcm_base->clken_pll_mpu,
333 0x000000F0, ptr->fsel << 4);
334 }
335
iva_init_34xx(u32 sil_index,u32 clk_index)336 static void iva_init_34xx(u32 sil_index, u32 clk_index)
337 {
338 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
339 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
340
341 /* Moving to the right sysclk and ES rev base */
342 ptr = ptr + (3 * clk_index) + sil_index;
343
344 /* IVA DPLL */
345 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
346 clrsetbits_le32(&prcm_base->clken_pll_iva2,
347 0x00000007, PLL_STOP);
348 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
349
350 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
351 clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
352 0x0000001F, ptr->m2);
353
354 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
355 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
356 0x0007FF00, ptr->m << 8);
357
358 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
359 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
360 0x0000007F, ptr->n);
361
362 /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
363 clrsetbits_le32(&prcm_base->clken_pll_iva2,
364 0x000000F0, ptr->fsel << 4);
365
366 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
367 clrsetbits_le32(&prcm_base->clken_pll_iva2,
368 0x00000007, PLL_LOCK);
369
370 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
371 }
372
373 /*
374 * OMAP3630 specific functions
375 */
376
dpll3_init_36xx(u32 sil_index,u32 clk_index)377 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
378 {
379 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
380 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
381 void (*f_lock_pll) (u32, u32, u32, u32);
382 int xip_safe, p0, p1, p2, p3;
383
384 xip_safe = is_running_in_sram();
385
386 /* Moving it to the right sysclk base */
387 ptr += clk_index;
388
389 if (xip_safe) {
390 /* CORE DPLL */
391
392 /* Select relock bypass: CM_CLKEN_PLL[0:2] */
393 clrsetbits_le32(&prcm_base->clken_pll,
394 0x00000007, PLL_FAST_RELOCK_BYPASS);
395 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
396 LDELAY);
397
398 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
399 clrsetbits_le32(&prcm_base->clksel1_emu,
400 0x001F0000, CORE_M3X2 << 16);
401
402 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
403 clrsetbits_le32(&prcm_base->clksel1_pll,
404 0xF8000000, ptr->m2 << 27);
405
406 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
407 clrsetbits_le32(&prcm_base->clksel1_pll,
408 0x07FF0000, ptr->m << 16);
409
410 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
411 clrsetbits_le32(&prcm_base->clksel1_pll,
412 0x00007F00, ptr->n << 8);
413
414 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
415 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
416
417 /* SSI */
418 clrsetbits_le32(&prcm_base->clksel_core,
419 0x00000F00, CORE_SSI_DIV << 8);
420 /* FSUSB */
421 clrsetbits_le32(&prcm_base->clksel_core,
422 0x00000030, CORE_FUSB_DIV << 4);
423 /* L4 */
424 clrsetbits_le32(&prcm_base->clksel_core,
425 0x0000000C, CORE_L4_DIV << 2);
426 /* L3 */
427 clrsetbits_le32(&prcm_base->clksel_core,
428 0x00000003, CORE_L3_DIV);
429 /* GFX */
430 clrsetbits_le32(&prcm_base->clksel_gfx,
431 0x00000007, GFX_DIV_36X);
432 /* RESET MGR */
433 clrsetbits_le32(&prcm_base->clksel_wkup,
434 0x00000006, WKUP_RSM << 1);
435 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
436 clrsetbits_le32(&prcm_base->clken_pll,
437 0x000000F0, ptr->fsel << 4);
438 /* LOCK MODE */
439 clrsetbits_le32(&prcm_base->clken_pll,
440 0x00000007, PLL_LOCK);
441
442 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
443 LDELAY);
444 } else if (is_running_in_flash()) {
445 /*
446 * if running from flash, jump to small relocated code
447 * area in SRAM.
448 */
449 f_lock_pll = (void *) (SRAM_CLK_CODE);
450
451 p0 = readl(&prcm_base->clken_pll);
452 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
453 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
454 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
455
456 p1 = readl(&prcm_base->clksel1_pll);
457 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
458 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
459 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
460 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
461 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
462 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
463 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
464 clrbits_le32(&p1, 0x00000040);
465
466 p2 = readl(&prcm_base->clksel_core);
467 /* SSI */
468 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
469 /* FSUSB */
470 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
471 /* L4 */
472 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
473 /* L3 */
474 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
475
476 p3 = (u32)&prcm_base->idlest_ckgen;
477
478 (*f_lock_pll) (p0, p1, p2, p3);
479 }
480 }
481
dpll4_init_36xx(u32 sil_index,u32 clk_index)482 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
483 {
484 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
485 struct dpll_per_36x_param *ptr;
486
487 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
488
489 /* Moving it to the right sysclk base */
490 ptr += clk_index;
491
492 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
493 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
494 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
495
496 /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
497 clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
498
499 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
500 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
501
502 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
503 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
504
505 /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
506 clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
507
508 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
509 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
510
511 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
512 clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
513
514 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
515 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
516
517 /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
518 clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
519
520 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
521 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
522 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
523 }
524
dpll5_init_36xx(u32 sil_index,u32 clk_index)525 static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
526 {
527 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
528 dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
529
530 /* Moving it to the right sysclk base */
531 ptr = ptr + clk_index;
532
533 /* PER2 DPLL (DPLL5) */
534 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
535 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
536 /* set M2 (usbtll_fck) */
537 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
538 /* set m (11-bit multiplier) */
539 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
540 /* set n (7-bit divider)*/
541 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
542 /* lock mode */
543 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
544 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
545 }
546
mpu_init_36xx(u32 sil_index,u32 clk_index)547 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
548 {
549 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
550 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
551
552 /* Moving to the right sysclk */
553 ptr += clk_index;
554
555 /* MPU DPLL (unlocked already */
556
557 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
558 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
559
560 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
561 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
562
563 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
564 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
565 }
566
iva_init_36xx(u32 sil_index,u32 clk_index)567 static void iva_init_36xx(u32 sil_index, u32 clk_index)
568 {
569 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
570 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
571
572 /* Moving to the right sysclk */
573 ptr += clk_index;
574
575 /* IVA DPLL */
576 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
577 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
578 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
579
580 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
581 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
582
583 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
584 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
585
586 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
587 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
588
589 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
590 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
591
592 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
593 }
594
595 /******************************************************************************
596 * prcm_init() - inits clocks for PRCM as defined in clocks.h
597 * called from SRAM, or Flash (using temp SRAM stack).
598 *****************************************************************************/
prcm_init(void)599 void prcm_init(void)
600 {
601 u32 osc_clk = 0, sys_clkin_sel;
602 u32 clk_index, sil_index = 0;
603 struct prm *prm_base = (struct prm *)PRM_BASE;
604 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
605
606 /*
607 * Gauge the input clock speed and find out the sys_clkin_sel
608 * value corresponding to the input clock.
609 */
610 osc_clk = get_osc_clk_speed();
611 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
612
613 /* set input crystal speed */
614 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
615
616 /* If the input clock is greater than 19.2M always divide/2 */
617 if (sys_clkin_sel > 2) {
618 /* input clock divider */
619 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
620 clk_index = sys_clkin_sel / 2;
621 } else {
622 /* input clock divider */
623 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
624 clk_index = sys_clkin_sel;
625 }
626
627 if (get_cpu_family() == CPU_OMAP36XX) {
628 /*
629 * In warm reset conditions on OMAP36xx/AM/DM37xx
630 * the rom code incorrectly sets the DPLL4 clock
631 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
632 * the AM/DM37x TRM explains that the /6.5 divider
633 * is used only when the input clock is 13MHz.
634 *
635 * If the part is in this cpu family *and* the input
636 * clock *is not* 13 MHz, then reset the DPLL4 clock
637 * input divider to /1 as it should never set to /6.5
638 * in this case.
639 */
640 if (sys_clkin_sel != 1) { /* 13 MHz */
641 /* Bit 8: DPLL4_CLKINP_DIV */
642 clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
643 }
644
645 /* Unlock MPU DPLL (slows things down, and needed later) */
646 clrsetbits_le32(&prcm_base->clken_pll_mpu,
647 0x00000007, PLL_LOW_POWER_BYPASS);
648 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
649 LDELAY);
650
651 dpll3_init_36xx(0, clk_index);
652 dpll4_init_36xx(0, clk_index);
653 dpll5_init_36xx(0, clk_index);
654 iva_init_36xx(0, clk_index);
655 mpu_init_36xx(0, clk_index);
656
657 /* Lock MPU DPLL to set frequency */
658 clrsetbits_le32(&prcm_base->clken_pll_mpu,
659 0x00000007, PLL_LOCK);
660 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
661 LDELAY);
662 } else {
663 /*
664 * The DPLL tables are defined according to sysclk value and
665 * silicon revision. The clk_index value will be used to get
666 * the values for that input sysclk from the DPLL param table
667 * and sil_index will get the values for that SysClk for the
668 * appropriate silicon rev.
669 */
670 if (((get_cpu_family() == CPU_OMAP34XX)
671 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
672 (get_cpu_family() == CPU_AM35XX))
673 sil_index = 1;
674
675 /* Unlock MPU DPLL (slows things down, and needed later) */
676 clrsetbits_le32(&prcm_base->clken_pll_mpu,
677 0x00000007, PLL_LOW_POWER_BYPASS);
678 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
679 LDELAY);
680
681 dpll3_init_34xx(sil_index, clk_index);
682 dpll4_init_34xx(sil_index, clk_index);
683 dpll5_init_34xx(sil_index, clk_index);
684 if (get_cpu_family() != CPU_AM35XX)
685 iva_init_34xx(sil_index, clk_index);
686
687 mpu_init_34xx(sil_index, clk_index);
688
689 /* Lock MPU DPLL to set frequency */
690 clrsetbits_le32(&prcm_base->clken_pll_mpu,
691 0x00000007, PLL_LOCK);
692 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
693 LDELAY);
694 }
695
696 /* Set up GPTimers to sys_clk source only */
697 setbits_le32(&prcm_base->clksel_per, 0x000000FF);
698 setbits_le32(&prcm_base->clksel_wkup, 1);
699
700 sdelay(5000);
701 }
702
703 /*
704 * Enable usb ehci uhh, tll clocks
705 */
ehci_clocks_enable(void)706 void ehci_clocks_enable(void)
707 {
708 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
709
710 /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
711 setbits_le32(&prcm_base->iclken_usbhost, 1);
712 /*
713 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
714 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
715 */
716 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
717 /* Enable USBTTL_ICLK */
718 setbits_le32(&prcm_base->iclken3_core, 0x00000004);
719 /* Enable USBTTL_FCLK */
720 setbits_le32(&prcm_base->fclken3_core, 0x00000004);
721 }
722
723 /******************************************************************************
724 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
725 *****************************************************************************/
per_clocks_enable(void)726 void per_clocks_enable(void)
727 {
728 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
729
730 /* Enable GP2 timer. */
731 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
732 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
733 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
734
735 /* Enable GP9 timer. */
736 setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
737 setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
738 setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
739
740 #ifdef CONFIG_SYS_NS16550
741 /* Enable UART1 clocks */
742 setbits_le32(&prcm_base->fclken1_core, 0x00002000);
743 setbits_le32(&prcm_base->iclken1_core, 0x00002000);
744
745 /* Enable UART2 clocks */
746 setbits_le32(&prcm_base->fclken1_core, 0x00004000);
747 setbits_le32(&prcm_base->iclken1_core, 0x00004000);
748
749 /* UART 3 Clocks */
750 setbits_le32(&prcm_base->fclken_per, 0x00000800);
751 setbits_le32(&prcm_base->iclken_per, 0x00000800);
752 #endif
753
754 #ifdef CONFIG_OMAP3_GPIO_2
755 setbits_le32(&prcm_base->fclken_per, 0x00002000);
756 setbits_le32(&prcm_base->iclken_per, 0x00002000);
757 #endif
758 #ifdef CONFIG_OMAP3_GPIO_3
759 setbits_le32(&prcm_base->fclken_per, 0x00004000);
760 setbits_le32(&prcm_base->iclken_per, 0x00004000);
761 #endif
762 #ifdef CONFIG_OMAP3_GPIO_4
763 setbits_le32(&prcm_base->fclken_per, 0x00008000);
764 setbits_le32(&prcm_base->iclken_per, 0x00008000);
765 #endif
766 #ifdef CONFIG_OMAP3_GPIO_5
767 setbits_le32(&prcm_base->fclken_per, 0x00010000);
768 setbits_le32(&prcm_base->iclken_per, 0x00010000);
769 #endif
770 #ifdef CONFIG_OMAP3_GPIO_6
771 setbits_le32(&prcm_base->fclken_per, 0x00020000);
772 setbits_le32(&prcm_base->iclken_per, 0x00020000);
773 #endif
774
775 #ifdef CONFIG_SYS_I2C_OMAP24XX
776 /* Turn on all 3 I2C clocks */
777 setbits_le32(&prcm_base->fclken1_core, 0x00038000);
778 setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
779 #endif
780 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
781 setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
782
783 if (get_cpu_family() != CPU_AM35XX)
784 out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
785
786 out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
787 out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
788 out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
789 out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
790 out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
791 out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
792 out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
793 if (get_cpu_family() != CPU_AM35XX) {
794 out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
795 out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
796 }
797
798 sdelay(1000);
799 }
800