1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Common functions for OMAP4/5 based boards 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2010 6*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author : 9*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 10*4882a593Smuzhiyun * Steve Sakoman <steve@sakoman.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <common.h> 16*4882a593Smuzhiyun #include <asm/cache.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Without LPAE short descriptors are used 22*4882a593Smuzhiyun * Set C - Cache Bit3 23*4882a593Smuzhiyun * Set B - Buffer Bit2 24*4882a593Smuzhiyun * The last 2 bits set to 0b10 25*4882a593Smuzhiyun * Do Not set XN bit4 26*4882a593Smuzhiyun * So value is 0xe 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * With LPAE cache configuration happens via MAIR0 register 29*4882a593Smuzhiyun * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. 30*4882a593Smuzhiyun * 0xFF maps to Cache writeback with Read and Write Allocate set 31*4882a593Smuzhiyun * The bits[1:0] should have the value 0b01 for the first level 32*4882a593Smuzhiyun * descriptor. 33*4882a593Smuzhiyun * So the value is 0xd 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #ifdef CONFIG_ARMV7_LPAE 37*4882a593Smuzhiyun #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC 38*4882a593Smuzhiyun #else 39*4882a593Smuzhiyun #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define ARMV7_DOMAIN_CLIENT 1 43*4882a593Smuzhiyun #define ARMV7_DOMAIN_MASK (0x3 << 0) 44*4882a593Smuzhiyun enable_caches(void)45*4882a593Smuzhiyunvoid enable_caches(void) 46*4882a593Smuzhiyun { 47*4882a593Smuzhiyun /* Enable D-cache. I-cache is already enabled in start.S */ 48*4882a593Smuzhiyun dcache_enable(); 49*4882a593Smuzhiyun } 50*4882a593Smuzhiyun dram_bank_mmu_setup(int bank)51*4882a593Smuzhiyunvoid dram_bank_mmu_setup(int bank) 52*4882a593Smuzhiyun { 53*4882a593Smuzhiyun bd_t *bd = gd->bd; 54*4882a593Smuzhiyun int i; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; 57*4882a593Smuzhiyun u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; 58*4882a593Smuzhiyun u32 end = start + size; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun debug("%s: bank: %d\n", __func__, bank); 61*4882a593Smuzhiyun for (i = start; i < end; i++) 62*4882a593Smuzhiyun set_section_dcache(i, ARMV7_DCACHE_POLICY); 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun arm_init_domains(void)65*4882a593Smuzhiyunvoid arm_init_domains(void) 66*4882a593Smuzhiyun { 67*4882a593Smuzhiyun u32 reg; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun reg = get_dacr(); 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * Set DOMAIN to client access so that all permissions 72*4882a593Smuzhiyun * set in pagetables are validated by the mmu. 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun reg &= ~ARMV7_DOMAIN_MASK; 75*4882a593Smuzhiyun reg |= ARMV7_DOMAIN_CLIENT; 76*4882a593Smuzhiyun set_dacr(reg); 77*4882a593Smuzhiyun } 78