1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Board specific setup info 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2010 5*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author : 8*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <config.h> 14*4882a593Smuzhiyun#include <asm/arch/omap.h> 15*4882a593Smuzhiyun#include <asm/omap_common.h> 16*4882a593Smuzhiyun#include <asm/arch/spl.h> 17*4882a593Smuzhiyun#include <linux/linkage.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun.arch_extension sec 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun#ifdef CONFIG_SPL 22*4882a593SmuzhiyunENTRY(save_boot_params) 23*4882a593Smuzhiyun ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS 24*4882a593Smuzhiyun str r0, [r1] 25*4882a593Smuzhiyun b save_boot_params_ret 26*4882a593SmuzhiyunENDPROC(save_boot_params) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) 29*4882a593SmuzhiyunENTRY(switch_to_hypervisor) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun/* 32*4882a593Smuzhiyun * Switch to hypervisor mode 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun adr r0, save_sp 35*4882a593Smuzhiyun str sp, [r0] 36*4882a593Smuzhiyun adr r1, restore_from_hyp 37*4882a593Smuzhiyun ldr r0, =0x102 38*4882a593Smuzhiyun b omap_smc1 39*4882a593Smuzhiyunrestore_from_hyp: 40*4882a593Smuzhiyun adr r0, save_sp 41*4882a593Smuzhiyun ldr sp, [r0] 42*4882a593Smuzhiyun MRC p15, 4, R0, c1, c0, 0 43*4882a593Smuzhiyun ldr r1, =0X1004 @Set cache enable bits for hypervisor mode 44*4882a593Smuzhiyun orr r0, r0, r1 45*4882a593Smuzhiyun MCR p15, 4, R0, c1, c0, 0 46*4882a593Smuzhiyun b switch_to_hypervisor_ret 47*4882a593Smuzhiyunsave_sp: 48*4882a593Smuzhiyun .word 0x0 49*4882a593SmuzhiyunENDPROC(switch_to_hypervisor) 50*4882a593Smuzhiyun#endif 51*4882a593Smuzhiyun#endif 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunENTRY(omap_smc1) 54*4882a593Smuzhiyun push {r4-r12, lr} @ save registers - ROM code may pollute 55*4882a593Smuzhiyun @ our registers 56*4882a593Smuzhiyun mov r12, r0 @ Service 57*4882a593Smuzhiyun mov r0, r1 @ Argument 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun dsb 60*4882a593Smuzhiyun dmb 61*4882a593Smuzhiyun smc 0 @ SMC #0 to enter monitor mode 62*4882a593Smuzhiyun @ call ROM Code API for the service requested 63*4882a593Smuzhiyun pop {r4-r12, pc} 64*4882a593SmuzhiyunENDPROC(omap_smc1) 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunENTRY(omap_smc_sec) 67*4882a593Smuzhiyun push {r4-r12, lr} @ save registers - ROM code may pollute 68*4882a593Smuzhiyun @ our registers 69*4882a593Smuzhiyun mov r6, #0xFF @ Indicate new Task call 70*4882a593Smuzhiyun mov r12, #0x00 @ Secure Service ID in R12 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun dsb 73*4882a593Smuzhiyun dmb 74*4882a593Smuzhiyun smc 0 @ SMC #0 to enter monitor mode 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun b omap_smc_sec_end @ exit at end of the service execution 77*4882a593Smuzhiyun nop 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun @ In case of IRQ happening in Secure, then ARM will branch here. 80*4882a593Smuzhiyun @ At that moment, IRQ will be pending and ARM will jump to Non Secure 81*4882a593Smuzhiyun @ IRQ handler 82*4882a593Smuzhiyun mov r12, #0xFE 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun dsb 85*4882a593Smuzhiyun dmb 86*4882a593Smuzhiyun smc 0 @ SMC #0 to enter monitor mode 87*4882a593Smuzhiyun 88*4882a593Smuzhiyunomap_smc_sec_end: 89*4882a593Smuzhiyun pop {r4-r12, pc} 90*4882a593SmuzhiyunENDPROC(omap_smc_sec) 91