1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * emif4.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * AM33XX emif4 configuration file
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/arch/cpu.h>
13*4882a593Smuzhiyun #include <asm/arch/ddr_defs.h>
14*4882a593Smuzhiyun #include <asm/arch/hardware.h>
15*4882a593Smuzhiyun #include <asm/arch/clock.h>
16*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun #include <asm/emif.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static struct vtp_reg *vtpreg[2] = {
21*4882a593Smuzhiyun (struct vtp_reg *)VTP0_CTRL_ADDR,
22*4882a593Smuzhiyun (struct vtp_reg *)VTP1_CTRL_ADDR};
23*4882a593Smuzhiyun #ifdef CONFIG_AM33XX
24*4882a593Smuzhiyun static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun #ifdef CONFIG_AM43XX
27*4882a593Smuzhiyun static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
28*4882a593Smuzhiyun static struct cm_device_inst *cm_device =
29*4882a593Smuzhiyun (struct cm_device_inst *)CM_DEVICE_INST;
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #ifdef CONFIG_TI814X
config_dmm(const struct dmm_lisa_map_regs * regs)33*4882a593Smuzhiyun void config_dmm(const struct dmm_lisa_map_regs *regs)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct dmm_lisa_map_regs *hw_lisa_map_regs =
36*4882a593Smuzhiyun (struct dmm_lisa_map_regs *)DMM_BASE;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun enable_dmm_clocks();
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
41*4882a593Smuzhiyun writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
42*4882a593Smuzhiyun writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
43*4882a593Smuzhiyun writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
46*4882a593Smuzhiyun writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
47*4882a593Smuzhiyun writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
48*4882a593Smuzhiyun writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun
config_vtp(int nr)52*4882a593Smuzhiyun static void config_vtp(int nr)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
55*4882a593Smuzhiyun &vtpreg[nr]->vtp0ctrlreg);
56*4882a593Smuzhiyun writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
57*4882a593Smuzhiyun &vtpreg[nr]->vtp0ctrlreg);
58*4882a593Smuzhiyun writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
59*4882a593Smuzhiyun &vtpreg[nr]->vtp0ctrlreg);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Poll for READY */
62*4882a593Smuzhiyun while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
63*4882a593Smuzhiyun VTP_CTRL_READY)
64*4882a593Smuzhiyun ;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
ddr_pll_config(unsigned int ddrpll_m)67*4882a593Smuzhiyun void __weak ddr_pll_config(unsigned int ddrpll_m)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
config_ddr(unsigned int pll,const struct ctrl_ioregs * ioregs,const struct ddr_data * data,const struct cmd_control * ctrl,const struct emif_regs * regs,int nr)71*4882a593Smuzhiyun void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
72*4882a593Smuzhiyun const struct ddr_data *data, const struct cmd_control *ctrl,
73*4882a593Smuzhiyun const struct emif_regs *regs, int nr)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun ddr_pll_config(pll);
76*4882a593Smuzhiyun config_vtp(nr);
77*4882a593Smuzhiyun config_cmd_ctrl(ctrl, nr);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun config_ddr_data(data, nr);
80*4882a593Smuzhiyun #ifdef CONFIG_AM33XX
81*4882a593Smuzhiyun config_io_ctrl(ioregs);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* Set CKE to be controlled by EMIF/DDR PHY */
84*4882a593Smuzhiyun writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun #ifdef CONFIG_AM43XX
88*4882a593Smuzhiyun writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
89*4882a593Smuzhiyun while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
90*4882a593Smuzhiyun ;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun config_io_ctrl(ioregs);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Set CKE to be controlled by EMIF/DDR PHY */
95*4882a593Smuzhiyun writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
98*4882a593Smuzhiyun /* Allow EMIF to control DDR_RESET */
99*4882a593Smuzhiyun writel(0x00000000, &ddrctrl->ddrioctrl);
100*4882a593Smuzhiyun #endif
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Program EMIF instance */
103*4882a593Smuzhiyun config_ddr_phy(regs, nr);
104*4882a593Smuzhiyun set_sdram_timings(regs, nr);
105*4882a593Smuzhiyun if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
106*4882a593Smuzhiyun config_sdram_emif4d5(regs, nr);
107*4882a593Smuzhiyun else
108*4882a593Smuzhiyun config_sdram(regs, nr);
109*4882a593Smuzhiyun }
110