1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include <config.h> 6*4882a593Smuzhiyun#include <linux/linkage.h> 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunENTRY(save_boot_params) 9*4882a593Smuzhiyun stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */ 10*4882a593Smuzhiyun ldr r12, =CONFIG_SPL_BOOTROM_SAVE 11*4882a593Smuzhiyun str sp, [r12] 12*4882a593Smuzhiyun b save_boot_params_ret 13*4882a593SmuzhiyunENDPROC(save_boot_params) 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunENTRY(return_to_bootrom) 16*4882a593Smuzhiyun ldr r12, =CONFIG_SPL_BOOTROM_SAVE 17*4882a593Smuzhiyun ldr sp, [r12] 18*4882a593Smuzhiyun mov r0, #0x0 /* @ return value: 0x0 NO_ERR */ 19*4882a593Smuzhiyun ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */ 20*4882a593SmuzhiyunENDPROC(return_to_bootrom) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun/* 23*4882a593Smuzhiyun * cache_inv - invalidate Cache line 24*4882a593Smuzhiyun * r0 - dest 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun .global cache_inv 27*4882a593Smuzhiyun .type cache_inv, %function 28*4882a593Smuzhiyun cache_inv: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun stmfd sp!, {r1-r12} 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun mcr p15, 0, r0, c7, c6, 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun ldmfd sp!, {r1-r12} 35*4882a593Smuzhiyun bx lr 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun/* 39*4882a593Smuzhiyun * flush_l1_v6 - l1 cache clean invalidate 40*4882a593Smuzhiyun * r0 - dest 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun .global flush_l1_v6 43*4882a593Smuzhiyun .type flush_l1_v6, %function 44*4882a593Smuzhiyun flush_l1_v6: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun stmfd sp!, {r1-r12} 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */ 49*4882a593Smuzhiyun mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */ 50*4882a593Smuzhiyun mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ldmfd sp!, {r1-r12} 53*4882a593Smuzhiyun bx lr 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun/* 57*4882a593Smuzhiyun * flush_l1_v7 - l1 cache clean invalidate 58*4882a593Smuzhiyun * r0 - dest 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun .global flush_l1_v7 61*4882a593Smuzhiyun .type flush_l1_v7, %function 62*4882a593Smuzhiyun flush_l1_v7: 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun stmfd sp!, {r1-r12} 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun dmb /* @data memory barrier */ 67*4882a593Smuzhiyun mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */ 68*4882a593Smuzhiyun dsb /* @data sync barrier */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun ldmfd sp!, {r1-r12} 71*4882a593Smuzhiyun bx lr 72