1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MVEBU_CPU_H 10*4882a593Smuzhiyun #define _MVEBU_CPU_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/system.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) 17*4882a593Smuzhiyun #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum memory_bank { 20*4882a593Smuzhiyun BANK0, 21*4882a593Smuzhiyun BANK1, 22*4882a593Smuzhiyun BANK2, 23*4882a593Smuzhiyun BANK3 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun enum cpu_winen { 27*4882a593Smuzhiyun CPU_WIN_DISABLE, 28*4882a593Smuzhiyun CPU_WIN_ENABLE 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum cpu_target { 32*4882a593Smuzhiyun CPU_TARGET_DRAM = 0x0, 33*4882a593Smuzhiyun CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, 34*4882a593Smuzhiyun CPU_TARGET_ETH23 = 0x3, 35*4882a593Smuzhiyun CPU_TARGET_PCIE02 = 0x4, 36*4882a593Smuzhiyun CPU_TARGET_ETH01 = 0x7, 37*4882a593Smuzhiyun CPU_TARGET_PCIE13 = 0x8, 38*4882a593Smuzhiyun CPU_TARGET_SASRAM = 0x9, 39*4882a593Smuzhiyun CPU_TARGET_SATA01 = 0xa, /* A38X */ 40*4882a593Smuzhiyun CPU_TARGET_NAND = 0xd, 41*4882a593Smuzhiyun CPU_TARGET_SATA23_DFX = 0xe, /* A38X */ 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum cpu_attrib { 45*4882a593Smuzhiyun CPU_ATTR_SASRAM = 0x01, 46*4882a593Smuzhiyun CPU_ATTR_DRAM_CS0 = 0x0e, 47*4882a593Smuzhiyun CPU_ATTR_DRAM_CS1 = 0x0d, 48*4882a593Smuzhiyun CPU_ATTR_DRAM_CS2 = 0x0b, 49*4882a593Smuzhiyun CPU_ATTR_DRAM_CS3 = 0x07, 50*4882a593Smuzhiyun CPU_ATTR_NANDFLASH = 0x2f, 51*4882a593Smuzhiyun CPU_ATTR_SPIFLASH = 0x1e, 52*4882a593Smuzhiyun CPU_ATTR_SPI0_CS0 = 0x1e, 53*4882a593Smuzhiyun CPU_ATTR_SPI0_CS1 = 0x5e, 54*4882a593Smuzhiyun CPU_ATTR_SPI1_CS2 = 0x9a, 55*4882a593Smuzhiyun CPU_ATTR_BOOTROM = 0x1d, 56*4882a593Smuzhiyun CPU_ATTR_PCIE_IO = 0xe0, 57*4882a593Smuzhiyun CPU_ATTR_PCIE_MEM = 0xe8, 58*4882a593Smuzhiyun CPU_ATTR_DEV_CS0 = 0x3e, 59*4882a593Smuzhiyun CPU_ATTR_DEV_CS1 = 0x3d, 60*4882a593Smuzhiyun CPU_ATTR_DEV_CS2 = 0x3b, 61*4882a593Smuzhiyun CPU_ATTR_DEV_CS3 = 0x37, 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun enum { 65*4882a593Smuzhiyun MVEBU_SOC_AXP, 66*4882a593Smuzhiyun MVEBU_SOC_A375, 67*4882a593Smuzhiyun MVEBU_SOC_A38X, 68*4882a593Smuzhiyun MVEBU_SOC_UNKNOWN, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * Default Device Address MAP BAR values 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define MBUS_PCI_MEM_BASE 0xE8000000 75*4882a593Smuzhiyun #define MBUS_PCI_MEM_SIZE (128 << 20) 76*4882a593Smuzhiyun #define MBUS_PCI_IO_BASE 0xF1100000 77*4882a593Smuzhiyun #define MBUS_PCI_IO_SIZE (64 << 10) 78*4882a593Smuzhiyun #define MBUS_SPI_BASE 0xF4000000 79*4882a593Smuzhiyun #define MBUS_SPI_SIZE (8 << 20) 80*4882a593Smuzhiyun #define MBUS_BOOTROM_BASE 0xF8000000 81*4882a593Smuzhiyun #define MBUS_BOOTROM_SIZE (8 << 20) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct mbus_win { 84*4882a593Smuzhiyun u32 base; 85*4882a593Smuzhiyun u32 size; 86*4882a593Smuzhiyun u8 target; 87*4882a593Smuzhiyun u8 attr; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * System registers 92*4882a593Smuzhiyun * Ref: Datasheet sec:A.28 93*4882a593Smuzhiyun */ 94*4882a593Smuzhiyun struct mvebu_system_registers { 95*4882a593Smuzhiyun #if defined(CONFIG_ARMADA_375) 96*4882a593Smuzhiyun u8 pad1[0x54]; 97*4882a593Smuzhiyun #else 98*4882a593Smuzhiyun u8 pad1[0x60]; 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun u32 rstoutn_mask; /* 0x60 */ 101*4882a593Smuzhiyun u32 sys_soft_rst; /* 0x64 */ 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * GPIO Registers 106*4882a593Smuzhiyun * Ref: Datasheet sec:A.19 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun struct kwgpio_registers { 109*4882a593Smuzhiyun u32 dout; 110*4882a593Smuzhiyun u32 oe; 111*4882a593Smuzhiyun u32 blink_en; 112*4882a593Smuzhiyun u32 din_pol; 113*4882a593Smuzhiyun u32 din; 114*4882a593Smuzhiyun u32 irq_cause; 115*4882a593Smuzhiyun u32 irq_mask; 116*4882a593Smuzhiyun u32 irq_level; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun struct sar_freq_modes { 120*4882a593Smuzhiyun u8 val; 121*4882a593Smuzhiyun u8 ffc; /* Fabric Frequency Configuration */ 122*4882a593Smuzhiyun u32 p_clk; 123*4882a593Smuzhiyun u32 nb_clk; 124*4882a593Smuzhiyun u32 d_clk; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* Needed for dynamic (board-specific) mbus configuration */ 128*4882a593Smuzhiyun extern struct mvebu_mbus_state mbus_state; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * functions 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun unsigned int mvebu_sdram_bar(enum memory_bank bank); 134*4882a593Smuzhiyun unsigned int mvebu_sdram_bs(enum memory_bank bank); 135*4882a593Smuzhiyun void mvebu_sdram_size_adjust(enum memory_bank bank); 136*4882a593Smuzhiyun int mvebu_mbus_probe(struct mbus_win windows[], int count); 137*4882a593Smuzhiyun int mvebu_soc_family(void); 138*4882a593Smuzhiyun u32 mvebu_get_nand_clock(void); 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun void return_to_bootrom(void); 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun void get_sar_freq(struct sar_freq_modes *sar_freq); 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* 147*4882a593Smuzhiyun * Highspeed SERDES PHY config init, ported from bin_hdr 148*4882a593Smuzhiyun * to mainline U-Boot 149*4882a593Smuzhiyun */ 150*4882a593Smuzhiyun int serdes_phy_config(void); 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* 153*4882a593Smuzhiyun * DDR3 init / training code ported from Marvell bin_hdr. Now 154*4882a593Smuzhiyun * available in mainline U-Boot in: 155*4882a593Smuzhiyun * drivers/ddr/marvell 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun int ddr3_init(void); 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun struct mvebu_lcd_info { 160*4882a593Smuzhiyun u32 fb_base; 161*4882a593Smuzhiyun int x_res; 162*4882a593Smuzhiyun int y_res; 163*4882a593Smuzhiyun int x_fp; /* frontporch */ 164*4882a593Smuzhiyun int y_fp; 165*4882a593Smuzhiyun int x_bp; /* backporch */ 166*4882a593Smuzhiyun int y_bp; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info); 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * get_ref_clk 173*4882a593Smuzhiyun * 174*4882a593Smuzhiyun * return: reference clock in MHz (25 or 40) 175*4882a593Smuzhiyun */ 176*4882a593Smuzhiyun u32 get_ref_clk(void); 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 179*4882a593Smuzhiyun #endif /* _MVEBU_CPU_H */ 180