xref: /OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/efuse.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2015-2016 Reinhard Pfau <reinhard.pfau@gdsys.cc>
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <config.h>
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/cpu.h>
12*4882a593Smuzhiyun #include <asm/arch/efuse.h>
13*4882a593Smuzhiyun #include <asm/arch/soc.h>
14*4882a593Smuzhiyun #include <linux/mbus.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #if defined(CONFIG_MVEBU_EFUSE_FAKE)
17*4882a593Smuzhiyun #define DRY_RUN
18*4882a593Smuzhiyun #else
19*4882a593Smuzhiyun #undef DRY_RUN
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define MBUS_EFUSE_BASE 0xF6000000
23*4882a593Smuzhiyun #define MBUS_EFUSE_SIZE BIT(20)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define MVEBU_EFUSE_CONTROL (MVEBU_REGISTER(0xE4008))
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun enum {
28*4882a593Smuzhiyun 	MVEBU_EFUSE_CTRL_PROGRAM_ENABLE = (1 << 31),
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct mvebu_hd_efuse {
32*4882a593Smuzhiyun 	u32 bits_31_0;
33*4882a593Smuzhiyun 	u32 bits_63_32;
34*4882a593Smuzhiyun 	u32 bit64;
35*4882a593Smuzhiyun 	u32 reserved0;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #ifndef DRY_RUN
39*4882a593Smuzhiyun static struct mvebu_hd_efuse *efuses =
40*4882a593Smuzhiyun 	(struct mvebu_hd_efuse *)(MBUS_EFUSE_BASE + 0xF9000);
41*4882a593Smuzhiyun #else
42*4882a593Smuzhiyun static struct mvebu_hd_efuse efuses[EFUSE_LINE_MAX + 1];
43*4882a593Smuzhiyun #endif
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static int efuse_initialised;
46*4882a593Smuzhiyun 
get_efuse_line(int nr)47*4882a593Smuzhiyun static struct mvebu_hd_efuse *get_efuse_line(int nr)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	if (nr < 0 || nr > 63 || !efuse_initialised)
50*4882a593Smuzhiyun 		return NULL;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return efuses + nr;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
enable_efuse_program(void)55*4882a593Smuzhiyun static void enable_efuse_program(void)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun #ifndef DRY_RUN
58*4882a593Smuzhiyun 	setbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_CTRL_PROGRAM_ENABLE);
59*4882a593Smuzhiyun #endif
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
disable_efuse_program(void)62*4882a593Smuzhiyun static void disable_efuse_program(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun #ifndef DRY_RUN
65*4882a593Smuzhiyun 	clrbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_CTRL_PROGRAM_ENABLE);
66*4882a593Smuzhiyun #endif
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
do_prog_efuse(struct mvebu_hd_efuse * efuse,struct efuse_val * new_val,u32 mask0,u32 mask1)69*4882a593Smuzhiyun static int do_prog_efuse(struct mvebu_hd_efuse *efuse,
70*4882a593Smuzhiyun 			 struct efuse_val *new_val, u32 mask0, u32 mask1)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	struct efuse_val val;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	val.dwords.d[0] = readl(&efuse->bits_31_0);
75*4882a593Smuzhiyun 	val.dwords.d[1] = readl(&efuse->bits_63_32);
76*4882a593Smuzhiyun 	val.lock = readl(&efuse->bit64);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	if (val.lock & 1)
79*4882a593Smuzhiyun 		return -EPERM;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	val.dwords.d[0] |= (new_val->dwords.d[0] & mask0);
82*4882a593Smuzhiyun 	val.dwords.d[1] |= (new_val->dwords.d[1] & mask1);
83*4882a593Smuzhiyun 	val.lock |= new_val->lock;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	writel(val.dwords.d[0], &efuse->bits_31_0);
86*4882a593Smuzhiyun 	mdelay(1);
87*4882a593Smuzhiyun 	writel(val.dwords.d[1], &efuse->bits_63_32);
88*4882a593Smuzhiyun 	mdelay(1);
89*4882a593Smuzhiyun 	writel(val.lock, &efuse->bit64);
90*4882a593Smuzhiyun 	mdelay(5);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
prog_efuse(int nr,struct efuse_val * new_val,u32 mask0,u32 mask1)95*4882a593Smuzhiyun static int prog_efuse(int nr, struct efuse_val *new_val, u32 mask0, u32 mask1)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	struct mvebu_hd_efuse *efuse;
98*4882a593Smuzhiyun 	int res = 0;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	res = mvebu_efuse_init_hw();
101*4882a593Smuzhiyun 	if (res)
102*4882a593Smuzhiyun 		return res;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	efuse = get_efuse_line(nr);
105*4882a593Smuzhiyun 	if (!efuse)
106*4882a593Smuzhiyun 		return -ENODEV;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	if (!new_val)
109*4882a593Smuzhiyun 		return -EINVAL;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	/* only write a fuse line with lock bit */
112*4882a593Smuzhiyun 	if (!new_val->lock)
113*4882a593Smuzhiyun 		return -EINVAL;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	/* according to specs ECC protection bits must be 0 on write */
116*4882a593Smuzhiyun 	if (new_val->bytes.d[7] & 0xFE)
117*4882a593Smuzhiyun 		return -EINVAL;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	if (!new_val->dwords.d[0] && !new_val->dwords.d[1] && (mask0 | mask1))
120*4882a593Smuzhiyun 		return 0;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	enable_efuse_program();
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	res = do_prog_efuse(efuse, new_val, mask0, mask1);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	disable_efuse_program();
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return res;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
mvebu_efuse_init_hw(void)131*4882a593Smuzhiyun int mvebu_efuse_init_hw(void)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	int ret;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if (efuse_initialised)
136*4882a593Smuzhiyun 		return 0;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	ret = mvebu_mbus_add_window_by_id(
139*4882a593Smuzhiyun 		CPU_TARGET_SATA23_DFX, 0xA, MBUS_EFUSE_BASE, MBUS_EFUSE_SIZE);
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	if (ret)
142*4882a593Smuzhiyun 		return ret;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	efuse_initialised = 1;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
mvebu_read_efuse(int nr,struct efuse_val * val)149*4882a593Smuzhiyun int mvebu_read_efuse(int nr, struct efuse_val *val)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct mvebu_hd_efuse *efuse;
152*4882a593Smuzhiyun 	int res;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	res = mvebu_efuse_init_hw();
155*4882a593Smuzhiyun 	if (res)
156*4882a593Smuzhiyun 		return res;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	efuse = get_efuse_line(nr);
159*4882a593Smuzhiyun 	if (!efuse)
160*4882a593Smuzhiyun 		return -ENODEV;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	if (!val)
163*4882a593Smuzhiyun 		return -EINVAL;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	val->dwords.d[0] = readl(&efuse->bits_31_0);
166*4882a593Smuzhiyun 	val->dwords.d[1] = readl(&efuse->bits_63_32);
167*4882a593Smuzhiyun 	val->lock = readl(&efuse->bit64);
168*4882a593Smuzhiyun 	return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
mvebu_write_efuse(int nr,struct efuse_val * val)171*4882a593Smuzhiyun int mvebu_write_efuse(int nr, struct efuse_val *val)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	return prog_efuse(nr, val, ~0, ~0);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
mvebu_lock_efuse(int nr)176*4882a593Smuzhiyun int mvebu_lock_efuse(int nr)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct efuse_val val = {
179*4882a593Smuzhiyun 		.lock = 1,
180*4882a593Smuzhiyun 	};
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	return prog_efuse(nr, &val, 0, 0);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun /*
186*4882a593Smuzhiyun  * wrapper funcs providing the fuse API
187*4882a593Smuzhiyun  *
188*4882a593Smuzhiyun  * we use the following mapping:
189*4882a593Smuzhiyun  *   "bank" ->	eFuse line
190*4882a593Smuzhiyun  *   "word" ->	0: bits 0-31
191*4882a593Smuzhiyun  *		1: bits 32-63
192*4882a593Smuzhiyun  *		2: bit 64 (lock)
193*4882a593Smuzhiyun  */
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun static struct efuse_val prog_val;
196*4882a593Smuzhiyun static int valid_prog_words;
197*4882a593Smuzhiyun 
fuse_read(u32 bank,u32 word,u32 * val)198*4882a593Smuzhiyun int fuse_read(u32 bank, u32 word, u32 *val)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	struct efuse_val fuse_line;
201*4882a593Smuzhiyun 	int res;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	if (bank < EFUSE_LINE_MIN || bank > EFUSE_LINE_MAX || word > 2)
204*4882a593Smuzhiyun 		return -EINVAL;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	res = mvebu_read_efuse(bank, &fuse_line);
207*4882a593Smuzhiyun 	if (res)
208*4882a593Smuzhiyun 		return res;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	if (word < 2)
211*4882a593Smuzhiyun 		*val = fuse_line.dwords.d[word];
212*4882a593Smuzhiyun 	else
213*4882a593Smuzhiyun 		*val = fuse_line.lock;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	return res;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
fuse_sense(u32 bank,u32 word,u32 * val)218*4882a593Smuzhiyun int fuse_sense(u32 bank, u32 word, u32 *val)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	/* not supported */
221*4882a593Smuzhiyun 	return -ENOSYS;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
fuse_prog(u32 bank,u32 word,u32 val)224*4882a593Smuzhiyun int fuse_prog(u32 bank, u32 word, u32 val)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun 	int res = 0;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	/*
229*4882a593Smuzhiyun 	 * NOTE: Fuse line should be written as whole.
230*4882a593Smuzhiyun 	 * So how can we do that with this API?
231*4882a593Smuzhiyun 	 * For now: remember values for word == 0 and word == 1 and write the
232*4882a593Smuzhiyun 	 * whole line when word == 2.
233*4882a593Smuzhiyun 	 * This implies that we always require all 3 fuse prog cmds (one for
234*4882a593Smuzhiyun 	 * for each word) to write a single fuse line.
235*4882a593Smuzhiyun 	 * Exception is a single write to word 2 which will lock the fuse line.
236*4882a593Smuzhiyun 	 *
237*4882a593Smuzhiyun 	 * Hope that will be OK.
238*4882a593Smuzhiyun 	 */
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	if (bank < EFUSE_LINE_MIN || bank > EFUSE_LINE_MAX || word > 2)
241*4882a593Smuzhiyun 		return -EINVAL;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	if (word < 2) {
244*4882a593Smuzhiyun 		prog_val.dwords.d[word] = val;
245*4882a593Smuzhiyun 		valid_prog_words |= (1 << word);
246*4882a593Smuzhiyun 	} else if ((valid_prog_words & 3) == 0 && val) {
247*4882a593Smuzhiyun 		res = mvebu_lock_efuse(bank);
248*4882a593Smuzhiyun 		valid_prog_words = 0;
249*4882a593Smuzhiyun 	} else if ((valid_prog_words & 3) != 3 || !val) {
250*4882a593Smuzhiyun 		res = -EINVAL;
251*4882a593Smuzhiyun 	} else {
252*4882a593Smuzhiyun 		prog_val.lock = val != 0;
253*4882a593Smuzhiyun 		res = mvebu_write_efuse(bank, &prog_val);
254*4882a593Smuzhiyun 		valid_prog_words = 0;
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	return res;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun 
fuse_override(u32 bank,u32 word,u32 val)260*4882a593Smuzhiyun int fuse_override(u32 bank, u32 word, u32 val)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	/* not supported */
263*4882a593Smuzhiyun 	return -ENOSYS;
264*4882a593Smuzhiyun }
265