1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <fdtdec.h>
10*4882a593Smuzhiyun #include <linux/libfdt.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/system.h>
13*4882a593Smuzhiyun #include <asm/arch/cpu.h>
14*4882a593Smuzhiyun #include <asm/arch/soc.h>
15*4882a593Smuzhiyun #include <asm/armv8/mmu.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Armada 7k/8k */
20*4882a593Smuzhiyun #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
21*4882a593Smuzhiyun #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
22*4882a593Smuzhiyun #define RFU_SW_RESET_OFFSET 0
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun * The following table includes all memory regions for Armada 7k and
26*4882a593Smuzhiyun * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
27*4882a593Smuzhiyun * define these regions at the beginning of the struct so that they
28*4882a593Smuzhiyun * can be easier removed later dynamically if an Armada 7k device is detected.
29*4882a593Smuzhiyun * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define ARMADA_7K8K_COMMON_REGIONS_START 2
32*4882a593Smuzhiyun static struct mm_region mvebu_mem_map[] = {
33*4882a593Smuzhiyun /* Armada 80x0 memory regions include the CP1 (slave) units */
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun /* SRAM, MMIO regions - CP110 slave region */
36*4882a593Smuzhiyun .phys = 0xf4000000UL,
37*4882a593Smuzhiyun .virt = 0xf4000000UL,
38*4882a593Smuzhiyun .size = 0x02000000UL, /* 32MiB internal registers */
39*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
40*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE
41*4882a593Smuzhiyun },
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun /* PCI CP1 regions */
44*4882a593Smuzhiyun .phys = 0xfa000000UL,
45*4882a593Smuzhiyun .virt = 0xfa000000UL,
46*4882a593Smuzhiyun .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
47*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
48*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE
49*4882a593Smuzhiyun },
50*4882a593Smuzhiyun /* Armada 80x0 and 70x0 common memory regions start here */
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun /* RAM */
53*4882a593Smuzhiyun .phys = 0x0UL,
54*4882a593Smuzhiyun .virt = 0x0UL,
55*4882a593Smuzhiyun .size = 0x80000000UL,
56*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
57*4882a593Smuzhiyun PTE_BLOCK_INNER_SHARE
58*4882a593Smuzhiyun },
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun /* SRAM, MMIO regions - AP806 region */
61*4882a593Smuzhiyun .phys = 0xf0000000UL,
62*4882a593Smuzhiyun .virt = 0xf0000000UL,
63*4882a593Smuzhiyun .size = 0x01000000UL, /* 16MiB internal registers */
64*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE
66*4882a593Smuzhiyun },
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun /* SRAM, MMIO regions - CP110 master region */
69*4882a593Smuzhiyun .phys = 0xf2000000UL,
70*4882a593Smuzhiyun .virt = 0xf2000000UL,
71*4882a593Smuzhiyun .size = 0x02000000UL, /* 32MiB internal registers */
72*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
73*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun /* PCI CP0 regions */
77*4882a593Smuzhiyun .phys = 0xf6000000UL,
78*4882a593Smuzhiyun .virt = 0xf6000000UL,
79*4882a593Smuzhiyun .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
80*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
81*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 0,
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct mm_region *mem_map = mvebu_mem_map;
89*4882a593Smuzhiyun
enable_caches(void)90*4882a593Smuzhiyun void enable_caches(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * Armada 7k is not equipped with the CP110 slave CP. In case this
94*4882a593Smuzhiyun * code runs on an Armada 7k device, lets remove the CP110 slave
95*4882a593Smuzhiyun * entries from the memory mapping by moving the start to the
96*4882a593Smuzhiyun * common regions.
97*4882a593Smuzhiyun */
98*4882a593Smuzhiyun if (of_machine_is_compatible("marvell,armada7040"))
99*4882a593Smuzhiyun mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun icache_enable();
102*4882a593Smuzhiyun dcache_enable();
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
reset_cpu(ulong ignored)105*4882a593Smuzhiyun void reset_cpu(ulong ignored)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun u32 reg;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun reg = readl(RFU_GLOBAL_SW_RST);
110*4882a593Smuzhiyun reg &= ~(1 << RFU_SW_RESET_OFFSET);
111*4882a593Smuzhiyun writel(reg, RFU_GLOBAL_SW_RST);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * TODO - implement this functionality using platform
116*4882a593Smuzhiyun * clock driver once it gets available
117*4882a593Smuzhiyun * Return NAND clock in Hz
118*4882a593Smuzhiyun */
mvebu_get_nand_clock(void)119*4882a593Smuzhiyun u32 mvebu_get_nand_clock(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
122*4882a593Smuzhiyun unsigned long NF_CLOCK_SEL_MASK = 0x1;
123*4882a593Smuzhiyun u32 reg;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun reg = readl(NAND_FLASH_CLK_CTRL);
126*4882a593Smuzhiyun if (reg & NF_CLOCK_SEL_MASK)
127*4882a593Smuzhiyun return 400 * 1000000;
128*4882a593Smuzhiyun else
129*4882a593Smuzhiyun return 250 * 1000000;
130*4882a593Smuzhiyun }
131